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ADM3311EARS 参数 Datasheet PDF下载

ADM3311EARS图片预览
型号: ADM3311EARS
PDF下载: 下载PDF文件 查看货源
内容描述: 15千伏ESD保护, 2.7 V至3.6 V串行端口收发器与绿色Idle⑩ [15 kV ESD Protected, 2.7 V to 3.6 V Serial Port Transceivers with Green Idle⑩]
分类和应用:
文件页数/大小: 16 页 / 307 K
品牌: AD [ ANALOG DEVICES ]
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ADM3307E/ADM3310E/ADM3311E/ADM3312E/ADM3315E
3V
EN
INPUT
0V
V
OH
RECEIVER
OUTPUT
V
OL
V
OL
+ 0.1V
RECEIVER
INPUT
D1
R
IN
D2
Rx
t
DR
V
OH
– 0.1V
The transmitter outputs and receiver inputs have a similar protec-
tion structure. The receiver inputs can also dissipate some of the
energy through the internal 5 kW (or 22 kW for the ADM3310E)
resistor to GND as well as through the protection diodes.
Figure 5. Receiver Disable Timing
3V
EN
INPUT
0V
V
OH
RECEIVER
OUTPUT
V
OL
Figure 7a. Receiver Input Protection Scheme
t
ER
3V
0.4V
Tx
D1
D2
TRANSMITTER
OUTPUT
Figure 6. Receiver Enable Timing
High Baud Rate
The ADM33xxE features high slew rates, permitting data trans-
mission at rates well in excess of the EIA/RS-232E specifications.
RS-232 voltage levels are maintained at data rates up to 230 kbps
(460 kbps for ADM3307E) under worst-case loading conditions.
This allows for high speed data links between two terminals.
LAYOUT AND SUPPLY DECOUPLING
Figure 7b. Transmitter Output Protection Scheme
Because of the high frequencies at which the ADM33xxE oscillator
operates, particular care should be taken with printed circuit
board layout, with all traces being as short as possible and C1 to
C3 being connected as close to the device as possible. The use
of a ground plane under and around the device is also highly
recommended.
When the oscillator starts up during Green Idle operation, large
current pulses are taken from V
CC
. For this reason, V
CC
should be
decoupled with a parallel combination of 10
mF
tantalum and
0.1
mF
ceramic capacitors, mounted as close to the V
CC
pin as
possible.
Capacitors C1 to C3 can have values between 0.1
mF
and 1
mF.
Larger values give lower ripple. These capacitors can be either
electrolytic capacitors chosen for low equivalent series resistance
(ESR) or nonpolarized types, but the use of ceramic types is
highly recommended. If polarized electrolytic capacitors are
used, polarity must be observed (as shown by C1+).
ESD/EFT TRANSIENT PROTECTION SCHEME
The ADM3307E protection scheme is slightly different (see
Figures 8a and 8b). The receiver inputs, transmitter inputs, and
transmitter outputs contain two back-to-back high speed clamping
diodes. The receiver outputs (CMOS outputs), SD and
EN
pins
contain a single reverse biased high speed clamping diode. Under
normal operation with maximum CMOS signal levels, the receiver
output, SD, and
EN
protection diodes have no effect because
they are reversed biased. If, however, the voltage exceeds about
15 V, reverse breakdown occurs and the voltage is clamped at
this level. If the voltage reaches –0.7 V, the diode is forward
biased and the voltage is clamped at this level. The receiver inputs
can also dissipate some of the energy through the internal 5 kW
resistor to GND as well as through the protection diodes.
RECEIVER
INPUT
D1
R
IN
D2
Rx
D3
RECEIVER
OUTPUT
Figure 8a. ADM3307E Receiver Input Protection Scheme
The ADM33xxE uses protective clamping structures on all inputs
and outputs that clamp the voltage to a safe level and dissipate
the energy present in ESD (electrostatic) and EFT (electrical fast
transients) discharges. A simplified schematic of the protection
structure is shown below in Figures 7a and 7b (see Figures 8a and
8b for ADM3307E protection structure). Each input and output
contains two back-to-back high speed clamping diodes. During nor-
mal operation with maximum RS-232 signal levels, the diodes have
no effect as one or the other is reverse biased depending on the
polarity of the signal. If however the voltage exceeds about
±50
V,
reverse breakdown occurs and the voltage is clamped at this level.
The diodes are large p-n junctions designed to handle the
instantaneous current surge that can exceed several amperes.
TRANSMITTER
OUTPUT
D3
D4
Tx
D1
D2
TRANSMITTER
INPUT
Figure 8b. ADM3307E Transmitter Output Protection Scheme
The protection structures achieve ESD protection up to
±15
kV on
all RS-232 I/O lines (and all CMOS lines, including SD and
EN
for the ADM3307E). The methods used to test the protection
scheme are discussed later.
REV. G
–13–