ADM3202/ADM3222/ADM1385
+3.3V INPUT
0.1 F +
10V
T1
IN
2V/DIV
C1+
C1–
+3.3V TO +6.6V V
CC
VOLTAGE
V+
DOUBLER
V–
C3
+ 0.1 F
6.3V
C4
+ 0.1 F
10V
T1
OUT
+ C5
0.1 F
0.1 F +
10V
T1
OUT
5V/DIV
C2+ +6.6V TO –6.6V
VOLTAGE
INVERTER
C2–
T1
IN
CMOS
INPUTS
T2
IN
R1
OUT
R2
OUT
T1
EIA/TIA-232
OUTPUTS
T2
T2
OUT
R1
IN
EIA/TIA-232
INPUTS*
R2
GND
R2
IN
1 s/DIV
Figure 7. 230 kbps Data Transmission
GENERAL DESCRIPTION
R1
CMOS
OUTPUTS
The ADM3202/ADM3222/ADM1385 are RS-232 line drivers/
receivers. Step-up voltage converters coupled with level shifting
transmitters and receivers allow RS-232 levels to be developed
while operating from a single +3.3 V supply.
CMOS technology is used to keep the power dissipation to an
absolute minimum, allowing maximum battery life in portable
applications.
The ADM3202/ADM3222/ADM1385 is a modification, en-
hancement and improvement to the AD230–AD241 family and
its derivatives. It is essentially plug-in compatible and does not
have materially different applications.
CIRCUIT DESCRIPTION
0.1 F +
10V
C1+
C1–
ADM3202
*INTERNAL
5k PULL-DOWN RESISTOR
ON EACH RS-232 INPUT
+3.3V INPUT
+3.3V TO +6.6V V
CC
VOLTAGE
V+
DOUBLER
V–
C3
+ 0.1 F
6.3V
C4
+ 0.1 F
10V
T1
OUT
T2
OUT
R1
IN
R2
IN
+ C5
0.1 F
0.1 F +
10V
C2+ +6.6V TO –6.6V
VOLTAGE
INVERTER
C2–
T1
IN
CMOS
INPUTS
T2
IN
R1
OUT
R2
OUT
EN
T1
T2
EIA/TIA-232
OUTPUTS
The internal circuitry consists of three main sections. These are:
1. A charge pump voltage converter
2. 3.3 V logic to EIA-232 transmitters
3. EIA-232 to 5 V logic receivers.
Charge Pump DC-DC Voltage Converter
CMOS
OUTPUTS
R1
EIA/TIA-232
INPUTS*
R2
ADM3222
GND
SD
The charge pump voltage converter consists of a 200 kHz oscil-
lator and a switching matrix. The converter generates a
±
6.6 V
supply from the input +3.3 V level. This is done in two stages
using a switched capacitor technique as illustrated below. First,
the +3.3 V input supply is doubled to +6.6 V using capacitor
C1 as the charge storage element. The +6.6 V level is then
inverted to generate –6.6 V using C2 as the storage element. C3
is shown connected between V+ and V
CC
, but is equally effec-
tive if connected between V+ and GND.
Capacitors C3 and C4 are used to reduce the output ripple.
Their values are not critical and can be increased if desired.
Capacitor C3 is shown connected between V+ and V
CC
. It is
also acceptable to connect this capacitor between V+ and GND.
If desired, larger capacitors (up to 10
µF)
can be used for
capacitors C1–C4.
CMOS
INPUTS
*INTERNAL
5k PULL-DOWN RESISTOR
ON EACH RS-232 INPUT
+3.3V INPUT
0.1 F +
10V
C1+
C1–
+3.3V TO +6.6V V
CC
VOLTAGE
V+
DOUBLER
V–
C4
+ 0.1 F
10V
+
+ C5
0.1 F
C3
0.1 F
6.3V
0.1 F +
10V
C2+ +6.6V TO –6.6V
VOLTAGE
INVERTER
C2–
T1
IN
T2
IN
R1
OUT
R2
OUT
DD
T1
T1
OUT
T2
OUT
R1
IN
R2
IN
EIA/TIA-232
INPUTS*
EIA/TIA-232
OUTPUTS
T2
R1
CMOS
OUTPUTS
R2
ADM1385
GND
SD
*INTERNAL
5k PULL-DOWN RESISTOR
ON EACH RS-232 INPUT
Figure 8. Typical Operating Circuits
–6–
REV. A
AD [ ANALOG DEVICES ]
