ADM1026
Chassis Intrusion Input
General-Purpose I/O Pins (Open Drain)
The chassis intrusion input is an active high input intended for
detection and signaling of unauthorized tampering with the
system. When this input goes high, the event is latched in Bit 6
of Status Register 4, and an interrupt is generated. The bit
remains set until cleared by writing a 1 to CI clear, Bit 1 of
Configuration Register 3 (05h), as long as battery voltage is
connected to the VBAT input. The CI clear bit itself is cleared by
writing a 0 to it.
The ADM1026 has eight pins that are dedicated to general-
purpose logic input/output (Pins 1, 2, and 43 to 48), eight pins
that can be configured as general-purpose logic pins or fan
speed inputs (Pins 3 to 6, and 9 to 12), and one pin that can
be configured as GPIO16 or the bidirectional
pin
THERM
(Pin 42). The GPIO/FAN pins are configured as general-
purpose logic pins by setting Bits 0 to 7 of Configuration
Register 2 (Address 01h). Pin 42 is configured as GPIO16 by
setting Bit 0 of Configuration Register 3, or as the
function by clearing this bit.
THERM
The CI input detects chassis intrusion events even when the
ADM1026 is powered off (provided battery voltage is applied to
VBAT) but does not immediately generate an interrupt. Once a
chassis intrusion event is detected and latched, an interrupt is
generated when the system is powered on.
Each GPIO pin has four data bits associated with it, two bits in
one of the GPIO configuration registers (Addresses 08h to 0Bh),
one in the GPIO status registers (Addresses 24h and 25h), and
one in the GPIO mask registers (Addresses 1Ch and 1Dh)
The actual detection of chassis intrusion is performed by an
external circuit that detects, for example, when the cover has
been removed. A wide variety of techniques may be used for the
detection, for example:
Setting a direction bit = 1 in one of the GPIO configuration
registers makes the corresponding GPIO pin an output.
Clearing the direction bit to 0 makes it an input.
•
A microswitch that opens or closes when the cover is
removed.
A reed switch operated by magnet fixed to the cover.
A hall-effect switch operated by magnet fixed to the cover.
A phototransistor that detects light when the cover is
removed.
Setting a polarity bit = 1 in one of the GPIO configuration
registers makes the corresponding GPIO pin active high.
Clearing the polarity bit to 0 makes it active low.
•
•
•
When a GPIO pin is configured as an input, the corresponding
bit in one of the GPIO status registers is read-only, and is set
when the input is asserted (“asserted” may be high or low
depending on the setting of the polarity bit).
The chassis intrusion input can also be used for other types of
alarm input. Figure 49 shows a temperature alarm circuit using
an AD22105 temperature switch sensor. This produces a low-
going output when the preset temperature is exceeded, so the
output is inverted by Q1 to make it compatible with the CI
input. Q1 can be almost any small-signal NPN transistor, or a
TTL or CMOS inverter gate may be used if one is available.
See the AD22105 data sheet on the Analog Devices, Inc.
When a GPIO pin is configured as an output, the corresponding
bit in one of the GPIO status registers becomes read/write.
Setting this bit then asserts the GPIO output. (Here again,
“asserted” may be high or low depending on the setting of the
polarity bit.)
The effect of a GPIO status register bit on the
output can
INT
website (www.analog.com) for information on selecting RSET
.
be masked out by setting the corresponding bit in one of the
GPIO mask registers. When the pin is configured as an output,
this bit is automatically masked to prevent the data written to
the status bit from causing an interrupt, with the exception of
GPIO16, which must be masked manually by setting Bit 7 of
Mask Register 4 (Reg 1Bh).
V
CC
R1
10kΩ
6
7
CI
AD22105
18
R
TEMPERATURE
SET
SENSOR
1
Q1
3
2
When configured as inputs, the GPIO pins may be connected to
external interrupt sources such as temperature sensors with
digital output. Another application of the GPIO pins would be
to monitor a processor’s voltage ID code (VID code).
Figure 49. Using the CI Input with a Temperature Sensor
Rev. A | Page 27 of 56
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