ADM1024
Configuration Registers:
Provide control and configuration.
Channel Mode Register:
Stores the data for the operating
modes of the input channels.
Address Pointer Register:
This register contains the address that
selects one of the other internal registers. When writing to the
ADM1024, the first byte of data is always a register address, which
is written to the Address Pointer Register.
Interrupt (INT) Status Registers:
Two registers to provide
status of each Interrupt event. These registers are also mirrored
at addresses 4Ch and 4Dh.
Interrupt (INT) Mask Registers:
Allow masking of individual
interrupt sources.
Temperature Configuration Register:
The configuration of
the temperature interrupt is controlled by the lower three bits of
this register.
VID/Fan Divisor Register:
The status of the VID0 to VID4
pins of the processor can be written to and read from these reg-
isters. Divisor values for fan-speed measurement are also stored
in this register.
Value and Limit Registers:
The results of analog voltage
inputs, temperature and fan speed measurements are stored in
these registers, along with their limit values.
Analog Output Register:
The code controlling the analog
output DAC is stored in this register.
Chassis Intrusion Clear Register:
A signal latched on the
chassis intrusion pin can be cleared by writing to this register.
SERIAL BUS INTERFACE
condition, and shift in the next eight bits, consisting of a
7-bit address (MSB first) plus an R/W bit, which determines
the direction of the data transfer, i.e., whether data will be
written to or read from the slave device.
The peripheral whose address corresponds to the transmitted
address responds by pulling the data line low during the low
period before the ninth clock pulse, known as the Acknowledge
Bit. All other devices on the bus now remain idle while the
selected device waits for data to be read from or written to it.
If the R/W bit is a 0, the master will write to the slave device.
If the R/W bit is a 1, the master will read from the slave device.
2. Data is sent over the serial bus in sequences of nine clock
pulses, eight bits of data followed by an Acknowledge Bit
from the slave device. Transitions on the data line must occur
during the low period of the clock signal and remain stable
during the high period, as a low-to-high transition when the
clock is high may be interpreted as a STOP signal. The number
of data bytes that can be transmitted over the serial bus in
a single READ or WRITE operation is limited only by what the
master and slave devices can handle.
3. When all data bytes have been read or written, stop conditions
are established. In WRITE mode, the master will pull the
data line high during the 10th clock pulse to assert a STOP
condition. In READ mode, the master device will override
the acknowledge bit by pulling the data line high during the
low period before the ninth clock pulse. This is known as No
Acknowledge. The master will then take the data line low
during the low period before the tenth clock pulse, then high
during the tenth clock pulse to assert a STOP condition.
Any number of bytes of data may be transferred over the serial
bus in one operation, but it is not possible to mix read and write
in one operation because the type of operation is determined at
the beginning and cannot subsequently be changed without
starting a new operation.
In the case of the ADM1024, write operations contain either
one or two bytes, and read operations contain one byte and
perform the following functions.
To write data to one of the device data registers or read data
from it, the Address Pointer Register must be set so that the
correct data register is addressed, then data can be written into
that register or read from it. The first byte of a write operation
always contains an address that is stored in the Address Pointer
Register. If data is to be written to the device, the write operation
contains a second data byte that is written to the register
selected by the address pointer register. This is illustrated in
Figure 9a. The device address is sent over the bus followed by
R/W set to 0. This is followed by two data bytes. The first data
byte is the address of the internal data register to be written
to, which is stored in the Address Pointer Register. The second
data byte is the data to be written to the internal data register.
When reading data from a register there are two possibilities:
1. If the ADM1024’s Address Pointer Register value is unknown
or not the desired value, it is first necessary to set it to the
correct value before data can be read from the desired data
register. This is done by performing a write to the ADM1024
as before, but only the data byte containing the register address
is sent, as data is not to be written to the register. This is shown
in Figure 9b.
REV. 0
Control of the ADM1024 is carried out via the serial bus. The
ADM1024 is connected to this bus as a slave device, under the
control of a master device, e.g., ICH.
The ADM1024 has a 7-bit serial bus address. When the device
is powered up, it will do so with a default serial bus address. The
five MSBs of the address are set to 01011, the two LSBs are
determined by the logical states of Pin 1 (NTESTOUT/ADD).
This is a three-state input that can be grounded, connected to
V
CC
or left open-circuit to give three different addresses.
Table I. ADD Pin Truth Table
ADD Pin
GND
No Connect
V
CC
A1
1
0
0
A0
0
0
1
If ADD is left open-circuit the default address will be 0101100. ADD
is sampled only at power-up, so any changes made while power is
on will have no immediate effect.
The facility to make hardwired changes to A1 and A0 allows the
user to avoid conflicts with other devices sharing the same serial
bus, for example if more than one ADM1024 is used in a system.
The serial bus protocol operates as follows:
1. The master initiates data transfer by establishing a START
condition, defined as a high-to-low transition on the serial
data line SDA while the serial clock line, SCL, remains high.
This indicates that an address/data stream will follow. All slave
peripherals connected to the serial bus respond to the START
–8–
AD [ ANALOG DEVICES ]
