ADG451/ADG452/ADG453
120
AP P LICATIO N
V
V
V
= ؉15V
DD
Figure 11 illustrates a precise, fast, sample-and-hold circuit.
An AD845 is used as the input buffer while the output
operational amplifier is an AD711. During the track mode,
SW1 is closed and the output VOUT follows the input signal
= –15V
SS
100
= ؉5V
L
R
= 50⍀
LOAD
80
60
VIN . In the hold mode, SW1 is opened and the signal is
held by the hold capacitor CH.
40
20
+5V
+15V
2200pF
+15V
SW2
S
C
D
D
C
+15V
AD845
AD711
–15V
1000pF
R
75⍀
C
0
100
V
OUT
V
IN
S
1k
10k
100k
1M
10M
100M
FREQUENCY – Hz
SW1
CH
2200pF
–15V
Figure 9. Crosstalk vs. Frequency
ADG451/
452/453
0
–0.5
–1.0
–15V
V
V
V
= ؉15V
DD
= –15V
SS
Figure 11. Fast, Accurate Sam ple-and-Hold Circuit
= ؉5V
L
Due to switch and capacitor leakage, the voltage on the
hold capacitor will decrease with time. The ADG451/
ADG452/ADG453 minimizes this droop due to its low
leakage specifications. The droop rate is further minimized
by the use of a polystyrene hold capacitor. The droop rate
for the circuit shown is typically 30 µV/µs.
–1.5
–2.0
–2.5
–3.0
–3.5
A second switch, SW2, that operates in parallel with SW1, is
included in this circuit to reduce pedestal error. Since both
switches will be at the same potential, they will have a differ-
ential effect on the op amp AD711, which will minimize
charge injection effects. Pedestal error is also reduced by the
compensation network RC and CC. This compensation net-
work reduces the hold time glitch while optimizing the ac-
quisition time. Using the illustrated op amps and component
values, the pedestal error has a maximum value of 5 mV over
the ±10 V input range. Both the acquisition and settling
times are 850 ns.
10
FREQUENCY – MHz
200
1
100
Figure 10. Frequency Response with Switch On
–8–
REV. A
ADI [ ADI ]
