ADG406/ADG407/ADG426
ADG426 TIMING DIAGRAMS
3V
0V
3V
WR
RS
50%
50%
50%
50%
0V
tW
tW
tS
tH
tOFF (RS)
3V
2V
V
0
A0, A1, A2, (A3)
0.8V
SWITCH
OUTPUT
0
0.8V
EN
0V
0V
Figure 4. Timing Sequence for Latching the Switch Address and Enable Inputs
Figure 5. Reset Pulse Width and Reset Turn Off Time
Figure 4 shows the timing sequence for latching the switch
address and enable inputs. The latches are level sensitive;
Figure 5 shows the reset pulse width, trs, and the reset turn off
RS
time, tOFF
(
).
WR
therefore, while
the switches respond to the address and enable inputs. This
WR
is held low, the latches are transparent and
Note that all digital input signals rise and fall times are
measured from 10% to 90% of 3 V; tR = tF = 20 ns.
input data is latched on the rising edge of
.
Rev. B | Page 7 of 20
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