Data Sheet
ADG211A/ADG212A
TERMINOLOGY
tOFF
RON
Delay time between the 50% and 90% points of the digital input
and switch off condition.
Ohmic resistance between the out and S terminals.
RON Match
tOPEN
Difference between the RON of any two channels.
Off time measured between 50% points of both switches, which
are connected as a multiplexer when switching from one
address state to another.
IS (Off)
Source terminal leakage current when the switch is off.
ID (Off)
VINL
Drain terminal leakage current when the switch is off.
Maximum input voltage for a logic low.
ID (On)
VINH
Leakage current that flows from the closed switch into the body.
Minimum input voltage for a logic high.
VD (VS)
I
INL (IINH)
Analog voltage on the D, S terminals.
Input current of the digital input.
CS (Off)
VDD
Switch input capacitance off condition.
Most positive voltage supply.
CD (Off)
VSS
Switch output capacitance off condition.
Most negative voltage supply.
CIN
VL
Digital input capacitance.
Logic supply voltage.
CD, CS (On)
IDD
Input or output capacitance when the switch is on.
Positive supply current.
tON
ISS
Delay time between the 50% and 90% points of the digital input
and switch on condition.
Negative supply current.
Rev. C | Page 9 of 16
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