Data Sheet
ADF4360-3
Table 7. Control Latch
OUTPUT
POWER
LEVEL
CORE
POWER
LEVEL
PRESCALER
VALUE
CURRENT
SETTING 2
CURRENT
SETTING 1
MUXOUT
CONTROL
CONTROL
BITS
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
P2
P1
PD2 PD1 CPI6 CPI5 CPI4 CPI3 CPI2 CPI1 PL2 PL1 MTLD CPG CP
PDP
M3
M2
M1
CR
PC2 PC1 C2 (0) C1 (0)
PC2
CORE POWER LEVEL
5mA
10mA
15mA
20mA
PC1
0
1
0
1
0
0
1
1
I
(mA)
PHASE DETECTOR
PDP POLARITY
CPI6
CPI3
CPI5
CPI2
CPI4
CPI1
CP
4.7kΩ
COUNTER
0
1
NEGATIVE
POSITIVE
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0.31
0.62
0.93
1.25
1.56
1.87
2.18
2.50
CR
OPERATION
0
1
NORMAL
R, A, B COUNTERS
HELD IN RESET
CHARGE PUMP
OUTPUT
NORMAL
CP
0
1
THREE-STATE
CP GAIN
CPG
0
1
CURRENT SETTING 1
CURRENT SETTING 2
MUTE-TILL-LOCK DETECT
DISABLED
ENABLED
MTLD
0
1
M3
0
0
M2
0
0
M1
0
1
OUTPUT
THREE-STATE OUTPUT
DIGITAL LOCK DETECT
(ACTIVE HIGH)
PL2
PL1
OUTPUT POWER LEVEL
CURRENT
POWER INTO 50Ω (USING 50Ω TO V
)
CC
0
0
1
1
0
1
0
1
3.5mA
5.0mA
7.5mA
11.0mA
–12dBm
–9dBm
–6dBm
–3dBm
0
0
1
1
0
1
N DIVIDER OUTPUT
DV
DD
R DIVIDER OUTPUT
N-CHANNEL OPEN-DRAIN
LOCK DETECT
1
1
0
0
0
1
SERIAL DATA OUTPUT
DGND
1
1
1
1
0
1
CE PIN
PD2
X
X
0
1
PD1
X
0
1
1
MODE
0
1
1
1
ASYNCHRONOUS POWER-DOWN
NORMAL OPERATION
ASYNCHRONOUS POWER-DOWN
SYNCHRONOUS POWER-DOWN
P2
0
P1
0
PRESCALER VALUE
8/9
0
1
1
1
0
1
16/17
32/33
32/33
Rev. C | Page 13 of 24
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