Data Sheet
CIRCUIT DESCRIPTION
REFERENCE INPUT SECTION
The reference input stage is shown in Figure 10. SW1 and SW2
are normally closed switches. SW3 is normally open. When
power-down is initiated, SW3 is closed, and SW1 and SW2 are
opened. This ensures that there is no loading of the REF
IN
pin
on power-down.
POWER-DOWN
CONTROL
100kΩ
TO R COUNTER
BUFFER
SW3
NO
04437-010
ADF4360-3
N = BP + A
13-BIT B
COUNTER
LOAD
FROM VCO
PRESCALER
P/P+1
MODULUS
CONTROL
LOAD
5-BIT A
COUNTER
04437-011
TO PFD
NC
REF
IN
NC
SW1
N DIVIDER
SW2
Figure 11. A and B Counters
R COUNTER
The 14-bit R counter allows the input reference frequency to
be divided down to produce the reference clock to the phase
frequency detector (PFD). Division ratios from 1 to 16,383 are
allowed.
Figure 10. Reference Input Stage
PRESCALER (P/P + 1)
The dual-modulus prescaler (P/P + 1), along with the A and B
counters, enables the large division ratio,
N
, to be realized
(N = BP + A). The dual-modulus prescaler, operating at CML
levels, takes the clock from the VCO and divides it down to a
manageable frequency for the CMOS A and B counters. The
prescaler is programmable. It can be set in software to 8/9,
16/17, or 32/33 and is based on a synchronous 4/5 core. There is
a minimum divide ratio possible for fully contiguous output
frequencies; this minimum is determined by P, the prescaler
value, and is given by (P
2
− P).
PFD AND CHARGE PUMP
The PFD takes inputs from the R counter and N counter
(N = BP + A) and produces an output proportional to the phase
and frequency difference between them. Figure 12 is a
simplified schematic. The PFD includes a programmable delay
element that controls the width of the antibacklash pulse. This
pulse ensures that there is no dead zone in the PFD transfer
function and minimizes phase noise and reference spurs. Two
bits in the R counter latch, ABP2 and ABP1, control the width
of the pulse (see Table 9).
V
P
CHARGE
PUMP
A AND B COUNTERS
The A and B CMOS counters combine with the dual-modulus
prescaler to allow a wide range division ratio in the PLL
feedback counter. The counters are specified to work when the
prescaler output is 300 MHz or less. Thus, with a VCO
frequency of 2.5 GHz, a prescaler value of 16/17 is valid, but a
value of 8/9 is not valid.
HI
D1
U1
Q1
UP
R DIVIDER
CLR1
Pulse Swallow Function
The A and B counters, in conjunction with the dual-modulus
prescaler, make it possible to generate output frequencies that
are spaced only by the reference frequency divided by R. The
VCO frequency equation is
HI
D2
U2
N DIVIDER
PROGRAMMABLE
DELAY
U3
CP
ABP1
CLR2
Q2
ABP2
DOWN
f
VCO
= [
(
P
×
B
)
+
A
] ×
f
REFIN
/
R
where:
f
VCO
is the output frequency of the VCO.
P
is the preset modulus of the dual-modulus prescaler (8/9,
16/17, and so on).
B
is the preset divide ratio of the binary 13-bit counter (3 to 8191).
A
is the preset divide ratio of the binary 5-bit swallow counter (0 to 31).
f
REFIN
is the external reference frequency oscillator.
CPGND
R DIVIDER
N DIVIDER
CP OUTPUT
Figure 12. PFD Simplified Schematic and Timing (In Lock)
Rev. C | Page 9 of 24
04437-012
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