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ADF4113BRU-REEL 参数 Datasheet PDF下载

ADF4113BRU-REEL图片预览
型号: ADF4113BRU-REEL
PDF下载: 下载PDF文件 查看货源
内容描述: [IC PLL FREQUENCY SYNTHESIZER, 4000 MHz, PDSO16, MO-153AB, TSSOP-16, PLL or Frequency Synthesis Circuit]
分类和应用: 信息通信管理光电二极管
文件页数/大小: 28 页 / 437 K
品牌: ADI [ ADI ]
 浏览型号ADF4113BRU-REEL的Datasheet PDF文件第18页浏览型号ADF4113BRU-REEL的Datasheet PDF文件第19页浏览型号ADF4113BRU-REEL的Datasheet PDF文件第20页浏览型号ADF4113BRU-REEL的Datasheet PDF文件第21页浏览型号ADF4113BRU-REEL的Datasheet PDF文件第23页浏览型号ADF4113BRU-REEL的Datasheet PDF文件第24页浏览型号ADF4113BRU-REEL的Datasheet PDF文件第25页浏览型号ADF4113BRU-REEL的Datasheet PDF文件第26页  
ADF4110/ADF4111/ADF4112/ADF4113  
APPLICATIONS  
LOCAL OSCILLATOR FOR GSM BASE STATION TRANSMITTER  
Figure 33 shows the ADF4111/ADF4112/ADF4113 being used  
with a VCO to produce the LO for a GSM base station  
transmitter.  
All of these specifications are needed and used to come up with  
the loop filter component values shown in Figure 33.  
The loop filter output drives the VCO, which in turn is fed back  
to the RF input of the PLL synthesizer. It also drives the RF out-  
put terminal. A T-circuit configuration provides 50 Ω matching  
between the VCO output, the RF output, and the RFIN terminal  
of the synthesizer.  
The reference input signal is applied to the circuit at FREFIN  
and, in this case, is terminated in 50 Ω. A typical GSM system  
would have a 13 MHz TCXO driving the reference input with-  
out any 50 Ω termination. In order to have channel spacing of  
200 kHz (GSM standard), the reference input must be divided  
by 65, using the on-chip reference divider of the ADF4111/  
ADF4112/ADF4113.  
In a PLL system, it is important to know when the system is in  
lock. In Figure 33, this is accomplished by using the MUXOUT  
signal from the synthesizer. The MUXOUT pin can be pro-  
grammed to monitor various internal signals in the synthesizer.  
One of these is the LD or lock-detect signal.  
The charge pump output of the ADF4111/ADF4112/ADF4113  
(Pin 2) drives the loop filter. In calculating the loop filter  
component values, a number of items need to be considered. In  
this example, the loop filter was designed so that the overall  
phase margin for the system would be 45 degrees. Other PLL  
system specifications are  
KD = 5 mA  
KV = 12 MHz/V  
Loop Bandwidth = 20 kHz  
FREF = 200 kHz  
N = 4500  
Extra Reference Spur Attenuation = 10 dB  
V
V
DD  
P
RF  
OUT  
100pF  
18Ω  
18Ω  
16  
7
15  
100pF  
B
18Ω  
V
AV  
DV  
P
DD  
DD  
3.3kΩ  
P
V
CC  
1000pF  
1000pF  
C
2
CP  
FREF  
8
IN  
REF  
IN  
620pF  
1nF  
5.6kΩ  
1
VCO190-902T  
51Ω  
ADF4111  
ADF4112  
ADF4113  
8.2nF  
CE  
LOCK  
DETECT  
MUXOUT  
14  
CLK  
DATA  
LE  
100pF  
6
5
RF  
RF  
A
B
IN  
R
2
1
SET  
51Ω  
IN  
4.7kΩ  
100pF  
3
4
9
1
2
TO BE USED WHEN GENERATOR SOURCE IMPEDANCE IS 50.  
OPTIONAL MATCHING RESISTOR DEPENDING ON RF FREQUENCY.  
OUT  
DECOUPLING CAPACITORS ON AV , DV , AND V OF THE ADF411x  
DD  
DD  
P
AND ON THE POSITIVE SUPPLY OF THE VCO190-902T HAVE BEEN  
OMITTED FROM THE DIAGRAM TO INCREASE CLARITY.  
Figure 33. Local Oscillator for GSM Base Station  
Rev. C | Page 22 of 28  
 
 
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