ADF4110/ADF4111/ADF4112/ADF4113
Table 7. Reference Counter Latch Map
ANTI-
BACKLASH
WIDTH
TEST
MODE BITS
CONTROL
BITS
DLY
SYNC
14-BIT REFERENCE COUNTER
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9
DB8
R7
DB7
R6
DB6
R5
DB5
R4
DB4
R3
DB3
R2
DB2
DB1
DB0
DLY SYNC LDP
T2
T1
ABP2 ABP1 R14
R13
R12
R11 R10
R9
R8
R1 C2 (0) C1 (0)
X
X = DON'T
CARE
R14
0
R13
0
R12
••••••••••
••••••••• •
R3
R2
R1
1
DIVIDE RATIO
1
0
0
0
0
•
0
0
0
1
•
0
1
1
0
•
0
0
0
•
0
0
0
•
••••••••• •
••••••••• •
••••••••• •
••••••••• •
••••••••• •
••••••••• •
••••••••• •
••••••••• •
••••••••• •
••••••••• •
0
1
0
•
2
3
4
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
1
1
0
1
0
1
16380
16381
16382
16383
ABP2 ABP1 ANTIBACKLASH PULSE WIDTH
0
0
1
1
0
1
0
1
3.0ns
1.5ns
6.0ns
3.0ns
TEST MODE BITS SHOULD
BE SET TO 00 FOR NORMAL
OPERATION
OPERATION
LDP
0
THREE CONSECUTIVE CYCLES OF PHASE DELAY LESS THAN
15ns MUST OCCUR BEFORE LOCK DETECT IS SET.
FIVE CONSECUTIVE CYCLES OF PHASE DELAY LESS THAN
15ns MUST OCCUR BEFORE LOCK DETECT IS SET.
1
DLY SYNC
OPERATION
0
0
0
1
NORMAL OPERATION
OUTPUT OF PRESCALER IS RESYNCHRONIZED
WITH NONDELAYED VERSION OF RF INPUT
1
1
0
1
NORMAL OPERATION
OUTPUT OF PRESCALER IS RESYNCHRONIZED
WITH DELAYED VERSION OF RF INPUT
Rev. C | Page 15 of 28
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