ADF4106
N = BP + A
TO PFD
MUXOUT AND LOCK DETECT
13-BIT B
COUNTER
FROM RF
INPUT STAGE
PRESCALER
P/P + 1
MODULUS
CONTROL
N DIVIDER
LOAD
LOAD
6-BIT A
COUNTER
The output multiplexer on the ADF4106 allows the user to access
various internal points on the chip. The state of MUXOUT is
controlled by M3, M2, and M1 in the function latch. Table V
shows the full truth table. Figure 6 shows the MUXOUT section
in block diagram form.
Lock Detect
MUXOUT can be programmed for two types of lock detect:
digital lock detect and analog lock detect.
Digital lock detect is active high. When LDP in the R counter
latch is set to 0, digital lock detect is set high when the phase
error on three consecutive phase detector cycles is less than 15 ns.
With LDP set to 1, five consecutive cycles of less than 15 ns are
required to set the lock detect. It will stay set high until a phase
error of greater than 25 ns is detected on any subsequent PD cycle.
The N-channel open-drain analog lock detect should be operated
with an external pull-up resistor of 10 kΩ nominal. When lock
has been detected, this output will be high with narrow low-
going pulses.
DV
DD
Figure 4. A and B Counters
R COUNTER
The 14-bit R counter allows the input reference frequency to be
divided down to produce the reference clock to the phase fre-
quency detector (PFD). Division ratios from 1 to 16,383 are
allowed.
PHASE FREQUENCY DETECTOR AND CHARGE PUMP
The PFD takes inputs from the R counter and N counter (N =
BP + A) and produces an output proportional to the phase and
frequency difference between them. Figure 5 is a simplified
schematic. The PFD includes a programmable delay element
that controls the width of the antibacklash pulse. This pulse
ensures that there is no dead zone in the PFD transfer function
and minimizes phase noise and reference spurs. Two bits in the
reference counter latch, ABP2 and ABP1, control the width of
the pulse. See Table III.
V
P
CHARGE
PUMP
ANALOG LOCK DETECT
DIGITAL LOCK DETECT
R COUNTER OUTPUT
N COUNTER OUTPUT
SDOUT
MUX
CONTROL
MUXOUT
HI
D1
Q1
U1
UP
DGND
R DIVIDER
CLR1
Figure 6. MUXOUT Circuit
PROGRAMMABLE
DELAY
ABP2
ABP1
U3
CP
INPUT SHIFT REGISTER
HI
D2
Q2
U2
DOWN
N DIVIDER
CLR2
CPGND
The ADF4106 digital section includes a 24-bit input shift register,
a 14-bit R counter, and a 19-bit N counter, comprising a 6-bit A
counter and a 13-bit B counter. Data is clocked into the 24-bit
shift register on each rising edge of CLK. The data is clocked
in MSB first. Data is transferred from the shift register to one
of four latches on the rising edge of LE. The destination latch
is determined by the state of the two control bits (C2, C1) in
the shift register. These are the two LSBs, DB1 and DB0, as
shown in the timing diagram of Figure 1. The truth table for these
bits is shown in Table VI. Table I shows a summary of how
the latches are programmed.
Table I. C2, C1 Truth Table
R DIVIDER
N DIVIDER
CP OUTPUT
Control Bits
C2
C1
0
0
1
1
0
1
0
1
Data Latch
R Counter
N Counter (A and B)
Function Latch (Including Prescaler)
Initialization Latch
Figure 5. PFD Simplified Schematic and Timing (In Lock)
REV. A
–9–
AD [ ANALOG DEVICES ]
