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ADF4106BRUZ-RL 参数 Datasheet PDF下载

ADF4106BRUZ-RL图片预览
型号: ADF4106BRUZ-RL
PDF下载: 下载PDF文件 查看货源
内容描述: PLL频率合成器 [PLL Frequency Synthesizer]
分类和应用: 信号电路锁相环或频率合成电路光电二极管PC
文件页数/大小: 24 页 / 361 K
品牌: ADI [ ADI ]
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Data Sheet  
ADF4106  
PHASE FREQUENCY DETECTOR (PFD) AND  
CHARGE PUMP  
The N-channel, open-drain, analog lock detect should be  
operated with an external pull-up resistor of 10 kΩ nominal.  
When lock is detected, this output is high with narrow, low-  
going pulses.  
The PFD takes inputs from the R counter and N counter  
(N = BP + A) and produces an output proportional to the  
phase and frequency difference between them. Figure 20 is a  
simplified schematic. The PFD includes a programmable delay  
element that controls the width of the antibacklash pulse. This  
pulse ensures that there is no dead zone in the PFD transfer  
function and minimizes phase noise and reference spurs. Two  
bits in the reference counter latch, ABP2 and ABP1, control the  
width of the pulse. See Table 7.  
DV  
DD  
ANALOG LOCK DETECT  
DIGITAL LOCK DETECT  
R COUNTER OUTPUT  
N COUNTER OUTPUT  
SDOUT  
MUX  
CONTROL  
MUXOUT  
V
P
CHARGE  
PUMP  
UP  
Q1  
U1  
D1  
HI  
DGND  
R DIVIDER  
CLR1  
Figure 21. MUXOUT Circuit  
PROGRAMMABLE  
DELAY  
INPUT SHIFT REGISTER  
U3  
CP  
The ADF4106 digital section includes a 24-bit input shift  
ABP2  
ABP1  
register, a 14-bit R counter, and a 19-bit N counter, comprising a  
6-bit A counter and a 13-bit B counter. Data is clocked into the  
24-bit shift register on each rising edge of CLK. The data is  
clocked in MSB first. Data is transferred from the shift register  
to one of four latches on the rising edge of LE. The destination  
latch is determined by the state of the two control bits (C2, C1)  
in the shift register. These are the two LSBs, DB1 and DB0, as  
shown in the timing diagram of Figure 2. The truth table for  
these bits is shown in Table 5. Table 6 shows a summary of how  
the latches are programmed.  
CLR2  
D2 Q2  
DOWN  
HI  
U2  
N DIVIDER  
CPGND  
Figure 20. PFD Simplified Schematic  
MUXOUT AND LOCK DETECT  
The output multiplexer on the ADF4106 allows the user  
to access various internal points on the chip. The state of  
MUXOUT is controlled by M3, M2, and M1 in the function  
latch. Table 9 shows the full truth table. Figure 21 shows the  
MUXOUT section in block diagram form.  
Table 5. C1, C2 Truth Table  
Control Bits  
C2  
0
C1  
0
Data Latch  
R Counter  
Lock Detect  
0
1
1
1
0
1
N Counter (A and B)  
Function Latch (Including Prescaler)  
Initialization Latch  
MUXOUT can be programmed for two types of lock detect:  
digital lock detect and analog lock detect.  
Digital lock detect is active high. When LDP in the R counter  
latch is set to 0, digital lock detect is set high when the phase  
error on three consecutive phase detector cycles is less than  
15 ns. With LDP set to 1, five consecutive cycles of less than  
15 ns are required to set the lock detect. It stays set high until a  
phase error of greater than 25 ns is detected on any subsequent  
PD cycle.  
Rev. E | Page 11 of 24