Data Sheet
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
R
SET 1
CP
2
CPGND
3
AGND
4
16
15
ADF4106
V
P
DV
DD
MUXOUT
CPGND 1
AGND 2
AGND 3
RF
IN
B 4
RF
IN
A 5
20 CP
19 R
SET
18 V
P
17 DV
DD
16 DV
DD
PIN 1
INDICATOR
ADF4106
14
TOP VIEW
13
LE
(Not to Scale)
12
DATA
RF
IN
B
5
RF
IN
A
6
AV
DD 7
REF
IN 8
11
10
9
ADF4106
TOP VIEW
15 MUXOUT
14 LE
13 DATA
12 CLK
11 CE
CE
DGND
02720-003
NOTE: TRANSISTOR COUNT 6425 (CMOS),
303 (BIPOLAR).
NOTES
1. TRANSISTOR COUNT 6425 (CMOS),
303 (BIPOLAR).
2. THE EXPOSED PAD MUST BE
CONNECTED TO AGND.
AV
DD
6
AV
DD
7
REF
IN
8
DGND 9
DGND 10
CLK
Figure 3. 16-Lead TSSOP Pin Configuration
Figure 4. 20-Lead LFCSP_VQ Pin Configuration
Table 4. Pin Function Descriptions
Pin No.
TSSOP
1
Pin No.
LFCSP
19
Mnemonic
R
SET
Function
Connecting a resistor between this pin and CPGND sets the maximum charge pump output current.
The nominal voltage potential at the R
SET
pin is 0.66 V. The relationship between I
CP
and R
SET
is
25.5
I
CP MAX
=
R
SET
So, with R
SET
= 5.1 kΩ, I
CP MAX
= 5 mA.
Charge Pump Output. When enabled, this provides ±I
CP
to the external loop filter, which in turn
drives the external VCO.
Charge Pump Ground. This is the ground return path for the charge pump.
Analog Ground. This is the ground return path of the prescaler.
Complementary Input to the RF Prescaler. This point must be decoupled to the ground plane with
a small bypass capacitor, typically 100 pF. See Figure 18.
Input to the RF Prescaler. This small signal input is ac-coupled to the external VCO.
Analog Power Supply. This may range from 2.7 V to 3.3 V. Decoupling capacitors to the analog ground
plane should be placed as close as possible to this pin. AV
DD
must be the same value as DV
DD
.
Reference Input. This is a CMOS input with a nominal threshold of V
DD
/2 and a dc equivalent input
resistance of 100 kΩ. See Figure 18. This input can be driven from a TTL or CMOS crystal oscillator or
it can be ac-coupled.
Digital Ground.
Chip Enable. A logic low on this pin powers down the device and puts the charge pump output
into three-state mode. Taking the pin high powers up the device, depending on the status of the
power-down bit, F2.
Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The data is latched
into the 24-bit shift register on the CLK rising edge. This input is a high impedance CMOS input.
Serial Data Input. The serial data is loaded MSB first with the two LSBs being the control bits.
This input is a high impedance CMOS input.
Load Enable, CMOS Input. When LE goes high, the data stored in the shift registers is loaded into one
of the four latches with the latch being selected using the control bits.
This multiplexer output allows either the lock detect, the scaled RF, or the scaled reference frequency
to be accessed externally.
Digital Power Supply. This may range from 2.7 V to 3.3 V. Decoupling capacitors to the digital ground
plane should be placed as close as possible to this pin. DV
DD
must be the same value as AV
DD
.
Charge Pump Power Supply. This should be greater than or equal to V
DD
. In systems where V
DD
is 3 V,
it can be set to 5.5 V and used to drive a VCO with a tuning range of up to 5 V.
Exposed Pad. The exposed pad must be connected to AGND.
Rev. E | Page 7 of 24
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
20
1
2, 3
4
5
6, 7
8
9, 10
11
12
13
14
15
16, 17
18
CP
CPGND
AGND
RF
IN
B
RF
IN
A
AV
DD
REF
IN
DGND
CE
CLK
DATA
LE
MUXOUT
DV
DD
V
P
EP
02720-004
AD [ ANALOG DEVICES ]
