ADF4106
Data Sheet
ADSP2181 Interface
INTERFACING
Figure 24 shows the interface between the ADF4106 and the
ADSP21xx digital signal processor (DSP). The ADF4106
needs a 24-bit serial word for each latch write. The easiest way
to accomplish this using the ADSP21xx family is to use the
autobuffered transmit mode of operation with alternate
framing. This provides a means for transmitting an entire block
of serial data before an interrupt is generated. Set up the word
length for 8 bits and use three memory locations for each 24-bit
word. To program each 24-bit latch, store the three 8-bit bytes,
enable the autobuffered mode, and write to the transmit register
of the DSP. This last operation initiates the autobuffer transfer.
The ADF4106 has a simple SPI-compatible serial interface for
writing to the device. CLK, DATA, and LE control the data
transfer. When LE goes high, the 24 bits clocked into the input
register on each rising edge of CLK are transferred to the
appropriate latch. See Figure 2 for the timing diagram and
Table 5 for the latch truth table.
The maximum allowable serial clock rate is 20 MHz. This
means that the maximum update rate for the device is 833 kHz,
or one update every 1.2 µs. This is certainly more than adequate
for systems that have typical lock times in hundreds of
microseconds.
SCLOCK
MOSI
CLK
ADuC812 Interface
DATA
Figure 23 shows the interface between the ADF4106 and the
ADuC812 MicroConverter®. Since the ADuC812 is based on an
8051 core, this interface can be used with any 8051-based
microcontroller. The MicroConverter is set up for SPI master
mode with CPHA = 0. To initiate the operation, the I/O port
driving LE is brought low. Each latch of the ADF4106 needs a
24-bit word. This is accomplished by writing three 8-bit bytes
from the MicroConverter to the device. When the third byte
is written, the LE input should be brought high to complete
the transfer.
TFS
LE
CE
ADSP-21xx
ADF4106
I/O FLAGS
MUXOUT
(LOCK DETECT)
Figure 24. ADSP-21xx-to-ADF4106 Interface
PCB DESIGN GUIDELINES FOR CHIP SCALE
PACKAGE
The lands on the LFCSP (CP-20) are rectangular. The printed
circuit board (PCB) pad for these should be 0.1 mm longer than
the package land length and 0.05 mm wider than the package
land width. The land should be centered on the pad. This
ensures that the solder joint size is maximized. The bottom of
the LFCSP has a central thermal pad.
On first applying power to the ADF4106, it needs four writes
(one each to the initialization latch, function latch, R counter
latch, and N counter latch) for the output to become active.
I/O port lines on the ADuC812 are also used to control
power-down (CE input) and to detect lock (MUXOUT
configured as lock detect and polled by the port input).
The thermal pad on the PCB should be at least as large as this
exposed pad. On the PCB, there should be a clearance of at least
0.25 mm between the thermal pad and the inner edges of the
pad pattern. This ensures that shorting is avoided.
When operating in the mode described, the maximum
SCLOCK rate of the ADuC812 is 4 MHz. This means that
the maximum rate at which the output frequency can be
changed is 166 kHz.
Thermal vias may be used on the PCB thermal pad to improve
thermal performance of the package. If vias are used, they
should be incorporated in the thermal pad at 1.2 mm pitch grid.
The via diameter should be between 0.3 mm and 0.33 mm, and
the via barrel should be plated with 1 oz. copper to plug the via.
SCLOCK
MOSI
CLK
DATA
LE
CE
ADuC812
I/O PORTS
ADF4106
The user should connect the PCB thermal pad to AGND.
MUXOUT
(LOCK DETECT)
Figure 23. ADuC812-to-ADF4106 Interface
Rev. E | Page 20 of 24
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