ADF4001
CIRCUIT DESCRIPTION
FROM
N COUNTER LATCH
Reference Input Section
The reference input stage is shown in Figure 2. SW1 and SW2
are normally closed switches. SW3 is normally open. When
power-down is initiated, SW3 is closed and SW1 and SW2 are
opened. This ensures that there is no loading of the REFIN pin
on power-down.
13-BIT N
COUNTER
FROM RF
INPUT STAGE
TO PFD
Figure 4. N Counter
R Counter
POWER-DOWN
CONTROL
The 14-bit R counter allows the input reference frequency to be
divided down to produce the reference clock to the phase frequency
detector (PFD). Division ratios from 1 to 16,383 are allowed.
NC
100kꢁ
PHASE FREQUENCY DETECTOR (PFD) AND CHARGE
PUMP
SW2
The PFD takes inputs from the R counter and N counter and
produces an output proportional to the phase and frequency
difference between them. Figure 5 is a simplified schematic. The
PFD includes a programmable delay element which controls the
width of the antibacklash pulse. This pulse ensures that there is
no deadzone in the PFD transfer function and minimizes phase
noise and reference spurs. Two bits in the Reference Counter
Latch, ABP2 and ABP1 control the width of the pulse. See
Table III.
TO
REF
IN NC
R COUNTER
BUFFER
SW1
SW3
NO
Figure 2. Reference Input Stage
RF Input Stage
The RF input stage is shown in Figure 3. It is followed by a
two-stage limiting amplifier to generate the CML clock levels
needed for the N Counter buffer.
V
P
CHARGE
PUMP
UP
Q1
HI
D1
U1
1.6V
BIAS
GENERATOR
R DIVIDER
CLR1
AV
DD
CP
2kꢁ
2kꢁ
DELAY
U3
RF
A
IN
RF
B
IN
CLR2
D2
DOWN
HI
Q2
U2
N DIVIDER
CPGND
AGND
Figure 3. RF Input Stage
N Counter
R DIVIDER
The N CMOS counter allows a wide ranging division ratio
in the PLL feedback counter. Division ratios of 1 to 8191
are allowed.
N DIVIDER
N and R Relationship
CP OUTPUT
The N counter, in conjunction with the R Counter make it
possible to generate output frequencies that are spaced only by
the Reference Frequency divided by R. The equation for the
VCO frequency is as follows:
Figure 5. PFD Simplified Schematic and Timing (In Lock)
MUXOUT AND LOCK DETECT
f
VCO = N/R × fREFIN
The output multiplexer on the ADF4110 family allows the
user to access various internal points on the chip. The state of
MUXOUT is controlled by M3, M2, and M1 in the Function
Latch. Table V shows the full truth table. Figure 6 shows the
MUXOUT section in block diagram form.
fVCO
N
Output Frequency of external voltage-controlled oscil-
lator (VCO).
Preset Divide Ratio of binary 13-bit counter (1 to 8,191).
fREFIN External reference frequency oscillator.
R
Preset divide ratio of binary 14-bit programmable refer-
ence counter (1 to 16,383).
–6–
REV. 0
ADI [ ADI ]
