ADE7759
Test Circuits
V
V
DD
DD
I
100nF
100nF
RESET
10ꢄF
10ꢄF
100nF
100nF
RESET
10ꢄF
10ꢄF
I
di/dt CURRENT
SENSOR
AVDD DVDD
V1P
AVDD DVDD
V1P
DIN
DIN
1kꢁ
100ꢁ 1kꢁ
TO SPI BUS
(USED ONLY FOR
CALIBRATION)
33nF
DOUT
SCLK
CS
TO SPI BUS
(USED ONLY FOR
CALIBRATION)
33nF 33nF
DOUT
SCLK
CS
RB
1kꢁ
100ꢁ 1kꢁ
V1N
U1
V1N
U1
33nF
33nF
33nF
ADE7759
ADE7759
CLKOUT
CLKIN
CLKOUT
CLKIN
Y1
22pF
22pF
Y1
V2N
V2N
3.58MHz
3.58MHz
1kꢁ 33nF
600kꢁ
1kꢁ
33nF
33nF
22pF
22pF
600kꢁ
V2P
V2P
IRQ
SAG
ZX
IRQ
SAG
ZX
33nF
110V
1kꢁ
110V
1kꢁ
NOT CONNECTED
NOT CONNECTED
REF
REF
IN/OUT
IN/OUT
U3
CF
U3
100nF
CF
100nF
10ꢄF
10ꢄF
AGND DGND
AGND DGND
TO
FREQUENCY
COUNTER
TO
FREQUENCY
COUNTER
CT TURN RATIO = 1800:1
CHANNEL 2 GAIN = 1
CHANNEL 1 GAIN = 4
CHANNEL 2 GAIN = 1
GAIN (CH1)
RB
1
4
10ꢁ
2.5ꢁ
PS2501-1
PS2501-1
Test Circuit 1. Performance Curve (Integrator OFF)
Test Circuit 2. Performance Curve (Integrator ON)
ANALOG INPUTS
In addition to the PGA, Channel 1 also has a full-scale input
range selection for the ADC. The ADC analog input range
selection is also made using the Gain register—see Figure 2. As
mentioned previously the maximum differential input voltage is
0.5 V. However, by using Bits 3 and 4 in the Gain register, the
maximum ADC input voltage can be set to 0.5 V, 0.25 V, or
0.125 V. This is achieved by adjusting the ADC reference—see
Reference Circuit section. Table I summarizes the maximum
differential input signal level on Channel 1 for the various ADC
range and gain selections.
The ADE7759 has two fully differential voltage input channels.
The maximum differential input voltage for input pairs V1P/V1N
and V2P/V2N are 0.5 V. In addition, the maximum signal level
on analog inputs for V1P/V1N and V2P/V2N are 0.5 V with
respect to AGND.
Each analog input channel has a PGA (Programmable Gain
Amplifier) with possible gain selections of 1, 2, 4, 8, and 16.
The gain selections are made by writing to the Gain register—
see Figure 5. Bits 0 to 2 select the gain for the PGA in Channel 1
and the gain selection for the PGA in Channel 2 is made via
Bits 5 to 7. Figure 4 shows how a gain selection for Channel 1
is made using the Gain register.
Table I. Maximum Input Signal Levels for Channel 1
Max Signal
Channel 1
ADC Input Range Selection
0.5 V
0.25 V
0.125 V
GAIN[7:0]
0.5 V
0.25 V
0.125 V
0.0625 V
0.0313 V
0.0156 V
0.00781 V
Gain = 1
Gain = 2
Gain = 4
Gain = 8
Gain = 16
Gain = 1
Gain = 2
Gain = 4
Gain = 8
Gain = 16
Gain = 1
Gain = 2
Gain = 4
Gain = 8
Gain = 16
GAIN (K)
SELECTION
V1P
V
IN
K ꢅ V
IN
GAIN REGISTER*
CHANNEL 1 AND CHANNEL 2 PGA CONTROL
V1N
7
6
5
4
3
2
1
0
+
0
0
0
0
0
0
0
0
ADDR:
0AH
OFFSET ADJUST
(ꢃ50mV)
PGA 2 GAIN SELECT
000 = ꢅ1
PGA 1 GAIN SELECT
000 = ꢅ1
001 = ꢅ2
001 = ꢅ2
010 = ꢅ4
010 = ꢅ4
CH1OS[7:0]
011 = ꢅ8
011 = ꢅ8
BIT 0 to 5: SIGN MAGNITUDE CODED OFFSET CORRECTION
BIT 6: NOT USED
BIT 7: DIGITAL INTEGRATOR (ON = 1, OFF = 0; DEFAULT ON)
100 = ꢅ16
100 = ꢅ16
CHANNEL 1 FULL SCALE SELECT
00 = 0.5V
01 = 0.25V
10 = 0.125V
*REGISTER CONTENTS
SHOW POWER-ON DEFAULTS
Figure 4. PGA in Channel 1
Figure 5. Analog Gain Register
REV. 0
–11–
ADI [ ADI ]
