ADE7755
Figure 7 shows two typical connections for Channel V2. The first
option uses a PT (potential transformer) to provide complete
isolation from the power line. In the second option, the
ADE7755 is biased around the neutral wire, and a resistor divider
provides a voltage signal that is proportional to the line voltage.
Adjusting the ratio of Ra, Rb, and VR is also a convenient way of
carrying out a gain calibration on the meter.
HPF and Offset Effects
Figure 9 shows the effect of offsets on the real power calculation.
An offset on Channel 1 and Channel 2 will contribute a dc
component after multiplication. Since the dc component is
extracted by the LPF, it will accumulate as real power. If not
properly filtered, dc offsets will introduce error to the energy
accumulation. This problem is easily avoided by enabling the
HPF (i.e., Pin AC/DC is set logic high) in Channel 1. By
removing the offset from at least one channel, no error compo-
nent can be generated at dc by the multiplication. Error terms
at cos(wt) are removed by the LPF and the digital-to-frequency
conversion (see Digital-to-Frequency Conversion section).
V2P
V2N
Rf
CT
Cf
Cf
ꢃ660mV
Rf
AGND
Vcos wt + VOS ¥ Icos wt + IOS
=
PHASE NEUTRAL
(
)
(
)
{
}
{
}
Cf
V ¥ I
Ra
*
+ VOS ¥ IOS + VOS ¥ Icos wt + IOS ¥ Vcos wt
(
)
(
)
2
Rb
*
V2P
V2N
ꢃ660mV
VR
*
V ¥ I
+
¥ cos 2wt
(
)
Rf
2
Cf
*
*
Ra >> Rb + VR
Rb + VR = Rf
PHASE NEUTRAL
Figure 7. Typical Connections for Channel 2
POWER SUPPLY MONITOR
The ADE7755 contains an on-chip power supply monitor. The
Analog Supply (AVDD) is continuously monitored by the ADE7755.
If the supply is less than 4 V ± 5%, the ADE7755 will be reset.
This is useful to ensure correct device startup at power-up and
power-down. The power supply monitor has built in hysteresis
and filtering. This gives a high degree of immunity to false trig-
gering due to noisy supplies.
DC COMPONENT (INCLUDING ERROR TERM)
IS EXTRACTED BY THE LPF FOR REAL
POWER CALCULATION
V
ꢁ I
OS
OS
V ꢁ I
2
I
ꢁ V
OS
V
ꢁ I
OS
2ꢆ
FREQUENCY – RAD/S
0
ꢆ
In Figure 8, the trigger level is nominally set at 4 V. The toler-
ance on this trigger level is about ±5%. The power supply and
decoupling for the part should be such that the ripple at AVDD
does not exceed 5 V ± 5% as specified for normal operation.
Figure 9. Effect of Channel Offset on the Real Power
Calculation
The HPF in Channel 1 has an associated phase response that is
compensated for on-chip. The phase compensation is activated
when the HPF is enabled and is disabled when the HPF is not
activated. Figures 10 and 11 show the phase error between chan-
nels with the compensation network activated. The ADE7755 is
phase compensated up to 1 kHz as shown. This will ensure correct
active harmonic power calculation even at low power factors.
AV
DD
5V
4V
0V
TIME
INTERNAL
RESET
RESET
ACTIVE
RESET
Figure 8. On-Chip Power Supply Monitor
REV. 0
–12–
ADI [ ADI ]
