AD9959
For the configuration shown in Table 17, the profile (channel
word) register is chosen based on the 2-bit value presented to
Profile Pins [P1:P2] or [P3:P4].
MODULATION USING SDIO_x PINS FOR RU/RD
For RU/RD bits = 11, the SDIO_1, SDIO_2, and SDIO_3 pins
are available for RU/RD. In this mode, modulation levels of 2, 4,
and 16 are available. Note that the serial I/O port can be used only
in 1-bit serial mode.
For example, if PPC = 011, [P0:P1] = 11, and [P2:P3] = 01,
the contents of the Channel Word 3 register of Channel 1 are
presented to the output of Channel 1, and the contents of the
Channel Word 1 register of Channel 2 are presented to the
output of Channel 2. SDIO_1 and SDIO_2 provide the RU/RD
function.
Two-Level Modulation Using SDIO Pins for RU/RD
Table 15. Profile Pin and Channel Assignments in Two-Level
Modulation (RU/RD Enabled)
Profile Pin Config. (PPC)
(FR1[14:12])
16-Level Modulation Using SDIO Pins for RU/RD
P0
P1
P2
P3
The RU/RD bits = 11 (the SDIO_1 pin is available for RU/RD),
and the level is set to 16. See the pin assignments shown in
Table 18.
XXX
CH0
CH1
CH2
CH3
For the configuration in Table 15, each profile pin is dedicated
to a specific channel. In this case, the SDIO_x pins can be used
for the RU/RD function, as described in Table 16.
For the configuration shown in Table 18, the profile (channel
word) register is chosen based on the 4-bit value presented to
Profile Pins [P0:P3]. For example, if PPC = X10 and [P0:P3] =
1101, then the contents of the Channel Word 13 register of
Channel 2 is presented to the output of Channel 2. The SDIO_1
pin provides the RU/RD function.
Four-Level Modulation Using SDIO Pins for RU/RD
For RU/RD bits = 11 (the SDIO_1 and SDIO_2 pins are avail-
able for RU/RD), the modulation level is set to 4. See Table 17
for pin assignments, including SDIO_x pin assignments.
Table 16. Channel and SDIO_1/SDIO_2/SDIO_3 Pin Assignments for RU/RD Operation
SDIO_1
SDIO_2
SDIO_3
Description
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Triggers the ramp-up function for CH0
Triggers the ramp-down function for CH0
Triggers the ramp-up function for CH1
Triggers the ramp-down function for CH1
Triggers the ramp-up function for CH2
Triggers the ramp-down function for CH2
Triggers the ramp-up function for CH3
Triggers the ramp-down function for CH3
Table 17. Channel and Profile Pin Assignments, Including SDIO_1/SDIO_2/SDIO_3 Pin Assignments for RU/RD Operation
Profile Pin Configuration (PPC) (FR1[14:12])
P0
P1
P2
P3
SDIO_1
SDIO_2
SDIO_3
000
001
010
011
100
101
CH0
CH0
CH0
CH1
CH1
CH2
CH0
CH0
CH0
CH1
CH1
CH2
CH1
CH2
CH3
CH2
CH3
CH3
CH1
CH2
CH3
CH2
CH3
CH3
CH0 RU/RD
CH0 RU/RD
CH0 RU/RD
CH1 RU/RD
CH1 RU/RD
CH2 RU/RD
CH1 RU/RD
CH2 RU/RD
CH3 RU/RD
CH2 RU/RD
CH3 RU/RD
CH3 RU/RD
N/A
N/A
N/A
N/A
N/A
N/A
Table 18. Channel and Profile Pin Assignments, Including SDIO_1 Pin Assignments for RU/RD Operation
Profile Pin Configuration (PPC) (FR1[14:12])
P0
P1
P2
P3
SDIO_1
SDIO_2
SDIO_3
N/A
N/A
N/A
N/A
X00
X01
X10
X11
CH0
CH1
CH2
CH3
CH0
CH1
CH2
CH3
CH0
CH1
CH2
CH3
CH0
CH1
CH2
CH3
CH0 RU/RD
CH1 RU/RD
CH2 RU/RD
CH3 RU/RD
N/A
N/A
N/A
N/A
Rev. B | Page 24 of 44
ADI [ ADI ]
