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AD9959BCPZ-REEL71 参数 Datasheet PDF下载

AD9959BCPZ-REEL71图片预览
型号: AD9959BCPZ-REEL71
PDF下载: 下载PDF文件 查看货源
内容描述: 4通道, 500 MSPS DDS ,10位DAC [4-Channel, 500 MSPS DDS with 10-Bit DACs]
分类和应用: 数据分配系统
文件页数/大小: 44 页 / 721 K
品牌: ADI [ ADI ]
 浏览型号AD9959BCPZ-REEL71的Datasheet PDF文件第5页浏览型号AD9959BCPZ-REEL71的Datasheet PDF文件第6页浏览型号AD9959BCPZ-REEL71的Datasheet PDF文件第7页浏览型号AD9959BCPZ-REEL71的Datasheet PDF文件第8页浏览型号AD9959BCPZ-REEL71的Datasheet PDF文件第10页浏览型号AD9959BCPZ-REEL71的Datasheet PDF文件第11页浏览型号AD9959BCPZ-REEL71的Datasheet PDF文件第12页浏览型号AD9959BCPZ-REEL71的Datasheet PDF文件第13页  
AD9959  
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS  
SYNC_IN  
SYNC_OUT  
MASTER_RESET  
PWR_DWN_CTL  
AVDD  
1
2
3
4
5
6
7
8
9
PIN 1  
INDICATOR  
42 P2  
41 P1  
40 P0  
39 AVDD  
38 AGND  
37 AVDD  
36 CH1_IOUT  
35 CH1_IOUT  
34 AGND  
33 AVDD  
32 AGND  
31 AVDD  
30 CH0_IOUT  
29 CH0_IOUT  
AGND  
AD9959  
AVDD  
CH2_IOUT  
CH2_IOUT  
TOP VIEW  
(Not to Scale)  
AGND 10  
AVDD 11  
AGND 12  
CH3_IOUT 13  
14  
CH3_IOUT  
NC = NO CONNECT  
NOTES  
1. THE EXPOSED EPAD ON BOTTOM SIDE OF PACKAGE IS  
AN ELECTRICAL CONNECTION AND MUST BE  
SOLDERED TO GROUND.  
2. PIN 49 IS DVDD_I/O AND IS TIED TO 3.3V.  
Figure 3. Pin Configuration  
Table 3. Pin Function Descriptions  
Pin No.  
Mnemonic  
I/O1  
Description  
1
SYNC_IN  
I
Used to Synchronize Multiple AD9959 Devices. Connects to the SYNC_OUT pin of  
the master AD9959 device.  
2
3
SYNC_OUT  
O
I
Used to Synchronize Multiple AD9959 Devices. Connects to the SYNC_IN pin of the  
slave AD9959 devices.  
Active High Reset Pin. Asserting the MASTER_RESET pin forces the AD9959 internal  
registers to their default state, as described in the Register Maps and Bit Descriptions  
section.  
MASTER_RESET  
4
PWR_DWN_CTL  
AVDD  
I
I
External Power-Down Control.  
Analog Power Supply Pins (1.8 V).  
5, 7, 11, 15, 19, 21,  
26, 31, 33, 37, 39  
6, 10, 12, 16, 18, 20,  
25, 28, 32, 34, 38  
AGND  
I
Analog Ground Pins.  
45, 55  
44, 56  
8
DVDD  
DGND  
I
I
Digital Power Supply Pins (1.8 V).  
Digital Power Ground Pins.  
True DAC Output. Terminates into AVDD.  
Complementary DAC Output. Terminates into AVDD.  
True DAC Output. Terminates into AVDD.  
Complementary DAC Output. Terminates into AVDD.  
CH2_IOUT  
CH2_IOUT  
CH3_IOUT  
CH3_IOUT  
DAC_RSET  
O
O
O
O
I
9
13  
14  
17  
Establishes the Reference Current for All DACs. A 1.91 kΩ resistor (nominal) is  
connected from Pin 17 to AGND.  
22  
23  
REF_CLK  
REF_CLK  
I
I
Complementary Reference Clock/Oscillator Input. When the REF_CLK is operated  
in single-ended mode, this pin should be decoupled to AVDD or AGND with a  
0.1 μF capacitor.  
Reference Clock/Oscillator Input. When the REF_CLK is operated in single-ended  
mode, this is the input. See the Modes of Operation section for the reference clock  
configuration.  
Rev. B | Page 9 of 44