AD9959
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
DGND
DVDD
SYNC_CLK
SDIO_3
SDIO_2
SDIO_1
SDIO_0
DVDD_I/O
SCLK
CS
I/O_UPDATE
DVDD
DGND
P3
SYNC_IN
SYNC_OUT
MASTER_RESET
PWR_DWN_CTL
AVDD
AGND
AVDD
CH2_IOUT
CH2_IOUT
AGND
AVDD
AGND
CH3_IOUT
CH3_IOUT
56
55
54
53
52
51
50
49
48
47
46
45
44
43
1
2
3
4
5
6
7
8
9
10
11
12
13
14
PIN 1
INDICATOR
AD9959
TOP VIEW
(Not to Scale)
42
41
40
39
38
37
36
35
34
33
32
31
30
29
P2
P1
P0
AVDD
AGND
AVDD
CH1_IOUT
CH1_IOUT
AGND
AVDD
AGND
AVDD
CH0_IOUT
CH0_IOUT
NOTES
1. THE EXPOSED EPAD ON BOTTOM SIDE OF PACKAGE IS
AN ELECTRICAL CONNECTION AND MUST BE
SOLDERED TO GROUND.
2. PIN 49 IS DVDD_I/O AND IS TIED TO 3.3V.
AVDD
AGND
DAC_RSET
AGND
AVDD
AGND
AVDD
REF_CLK
REF_CLK
CLK_MODE_SEL
AGND
AVDD
LOOP_FILTER
AGND
NC = NO CONNECT
15
16
17
18
19
20
21
22
23
24
25
26
27
28
Figure 3. Pin Configuration
Table 3. Pin Function Descriptions
Pin No.
1
2
3
Mnemonic
SYNC_IN
SYNC_OUT
MASTER_RESET
I/O
I
O
I
Description
Used to Synchronize Multiple AD9959 Devices. Connects to the SYNC_OUT pin of
the master AD9959 device.
Used to Synchronize Multiple AD9959 Devices. Connects to the SYNC_IN pin of the
slave AD9959 devices.
Active High Reset Pin. Asserting the MASTER_RESET pin forces the AD9959 internal
registers to their default state, as described in the Register Maps and Bit Descriptions
section.
External Power-Down Control.
Analog Power Supply Pins (1.8 V).
Analog Ground Pins.
Digital Power Supply Pins (1.8 V).
Digital Power Ground Pins.
True DAC Output. Terminates into AVDD.
Complementary DAC Output. Terminates into AVDD.
True DAC Output. Terminates into AVDD.
Complementary DAC Output. Terminates into AVDD.
Establishes the Reference Current for All DACs. A 1.91 kΩ resistor (nominal) is
connected from Pin 17 to AGND.
Complementary Reference Clock/Oscillator Input. When the REF_CLK is operated
in single-ended mode, this pin should be decoupled to AVDD or AGND with a
0.1 μF capacitor.
Reference Clock/Oscillator Input. When the REF_CLK is operated in single-ended
mode, this is the input. See the Modes of Operation section for the reference clock
configuration.
Rev. B | Page 9 of 44
4
5, 7, 11, 15, 19, 21,
26, 31, 33, 37, 39
6, 10, 12, 16, 18, 20,
25, 28, 32, 34, 38
45, 55
44, 56
8
9
13
14
17
22
PWR_DWN_CTL
AVDD
AGND
DVDD
DGND
CH2_IOUT
CH2_IOUT
CH3_IOUT
CH3_IOUT
DAC_RSET
REF_CLK
I
I
I
I
I
O
O
O
O
I
I
23
REF_CLK
I
05246-003
AD [ ANALOG DEVICES ]
