AD9958
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
Residual Phase Noise @ 15.1 MHz (fOUT
)
w/REF_CLK Multiplier Enabled 20×
@ 1 kHz Offset
@ 10 kHz Offset
@ 100 kHz Offset
@ 1 MHz Offset
–127
–136
–139
–138
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
Residual Phase Noise @ 40.1 MHz (fOUT
)
w/REF_CLK Multiplier Enabled 20×
@ 1 kHz Offset
@ 10 kHz Offset
@ 100 kHz Offset
@ 1 MHz Offset
–117
–128
–132
–130
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
Residual Phase Noise @ 75.1 MHz (fOUT) w/REF_CLK
Multiplier Enabled 20×
@ 1 kHz Offset
@ 10 kHz Offset
@ 100 kHz Offset
@ 1 MHz Offset
–110
–121
–125
–123
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
Residual Phase Noise @ 100.3 MHz (fOUT) w/REF_CLK
Multiplier Enabled 20×
@ 1 kHz Offset
–107
–119
–121
–119
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
@ 10 kHz Offset
@ 100 kHz Offset
@ 1 MHz Offset
SERIAL PORT TIMING CHARACTERISTICS
Maximum Frequency Serial Clock (SCLK)
200
MHz
ns
Minimum SCLK Pulse Width Low (tPWL
)
1.6
2.2
2.2
0
Minimum SCLK Pulse Width High (tPWH
)
ns
Minimum Data Set-Up Time (tDS
Minimum Data Hold Time
)
ns
ns
Minimum CSB Set-Up Time (tPRE
)
1.0
12
ns
Minimum Data Valid Time for Read Operation
MISCELLANEOUS TIMING CHARACTERISTICS
Master_Reset Minimum Pulse Width
I/O_Update Minimum Pulse Width
Minimum Set-Up Time (I/O_Update to SYNC_CLK)
Minimum Hold Time (I/O_Update to SYNC_CLK)
Minimum Set-Up Time (Profile Inputs to SYNC_CLK)
Minimum Hold Time (Profile Inputs to SYNC_CLK)
Minimum Set-Up Time (SDIO Inputs to SYNC_CLK)
Minimum Hold Time (SDIO Inputs to SYNC_CLK)
Propagation Time Between REF_CLK and SYNC_CLK
CMOS LOGIC INPUTS
ns
1
Min pulse width = 1 sync clock period
Min pulse width = 1 sync clock period
Rising edge to rising edge
1
4.8
0
ns
ns
ns
ns
ns
ns
ns
Rising edge to rising edge
5.4
0
2.5
0
2.25
3.5
5.5
VIH
2.0
V
VIL
0.8
12
V
Logic 1 Current
3
µA
µA
pF
Logic 0 Current
−12
2
Input Capacitance
CMOS LOGIC OUTPUTS (1 mA Load)
VOH
2.7
V
V
VOL
0.4
POWER SUPPLY
315
350
380
420
mW
mW
Dominated by supply variation
Dominated by supply variation
Total Power Dissipation—Both Channels On, Single-
Tone Mode
Total Power Dissipation—Both Channels On, with
Sweep Accumulator
13
90
mW
mA
Total Power Dissipation—Full Power Down
IAVDD—Both Channels On, Single Tone Mode
105
Rev. 0 | Page 6 of 40
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