AD9883A
Data is read from the control registers of the AD9883A in a similar
manner. Reading requires two data transfer operations:
➥ Base Address Byte
➥ Data Byte to Base Address
➥ Data Byte to (Base Address + 1)
➥ Data Byte to (Base Address + 2)
➥ Data Byte to (Base Address + 3)
➥ Stop Signal
The base address must be written with the R/W Bit of the slave
address byte low to set up a sequential read operation.
Reading (the R/W Bit of the slave address byte high) begins at
the previously established base address. The address of the read
register autoincrements after each byte is transferred.
Read from one control register
➥ Start Signal
➥ Slave Address Byte (R/W Bit = Low)
➥ Base Address Byte
To terminate a read/write sequence to the AD9883A, a stop
signal must be sent. A stop signal comprises a low-to-high tran-
sition of SDA while SCL is high.
➥ Start Signal
➥ Slave Address Byte (R/W Bit = High)
➥ Data Byte from Base Address
➥ Stop Signal
A repeated start signal occurs when the master device driving
the serial interface generates a start signal without first generating
a stop signal to terminate the current communication. This is
used to change the mode of communication (read, write)
between the slave and master without releasing the serial
interface lines.
Read from four consecutive control registers
➥ Start Signal
➥ Slave Address Byte (R/W Bit = Low)
➥ Base Address Byte
Serial Interface Read/Write Examples
Write to one control register
➥ Start Signal
➥ Slave Address Byte (R/W Bit = Low)
➥ Base Address Byte
➥ Start Signal
➥ Slave Address Byte (R/W Bit = High)
➥ Data Byte from Base Address
➥ Data Byte from (Base Address + 1)
➥ Data Byte from (Base Address + 2)
➥ Data Byte from (Base Address + 3)
➥ Stop Signal
➥ Data Byte to Base Address
➥ Stop Signal
Write to four consecutive control registers
➥ Start Signal
➥ Slave Address Byte (R/W Bit = Low)
SDA
SCL
BIT 6 BIT 5 BIT 4
BIT 3 BIT 2 BIT 1 BIT 0
ACK
BIT 7
Figure 11. Serial Interface—Typical Byte Transfer
ACTIVITY
DETECT
SYNC STRIPPER
SYNC SEPARATOR
INTEGRATOR
NEGATIVE PEAK
CLAMP
COMP
SYNC
VSYNC
1/S
SOG
MUX 1
HSYNC IN
SOG OUT
PLL
ACTIVITY
DETECT
POLARITY
DETECT
HSYNC OUT
PIXEL CLOCK
HSYNC
HSYNC OUT
CLOCK
GENERATOR
MUX 2
MUX 3
COAST
COAST
POLARITY
DETECT
AD9883A
VSYNC IN
VSYNC OUT
ACTIVITY
DETECT
POLARITY
DETECT
MUX 4
Figure 12. Sync Processing Block Diagram
–23–
REV. B
ADI [ ADI ]
