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AD9856AST 参数 Datasheet PDF下载

AD9856AST图片预览
型号: AD9856AST
PDF下载: 下载PDF文件 查看货源
内容描述: CMOS 200 MHz的正交数字上变频器 [CMOS 200 MHz Quadrature Digital Upconverter]
分类和应用:
文件页数/大小: 32 页 / 432 K
品牌: AD [ ANALOG DEVICES ]
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AD9856–SPECIFICATIONS
Parameter
REF CLOCK INPUT CHARACTERISTICS
Frequency Range
REFCLK Multiplier Disabled
REFCLK Multiplier Enabled at 4×
REFCLK Multiplier Enabled at 20×
Duty Cycle
Input Capacitance
Input Impedance
DAC OUTPUT CHARACTERISTICS
Resolution
Full-Scale Output Current
Gain Error
Output Offset
Differential Nonlinearity
Integral Nonlinearity
Output Capacitance
Phase Noise @ 1 kHz Offset, 40 MHz A
OUT
REFCLK Multiplier Enabled at 20×
REFCLK Multiplier at 4×
REFCLK Multiplier Disabled
Voltage Compliance Range
Wideband SFDR:
1 MHz Analog Out
20 MHz Analog Out
42 MHz Analog Out
65 MHz Analog Out
80 MHz Analog Out
Narrowband SFDR: (± 100 kHz Window)
70 MHz Analog Out
(V
S
= +3 V 5%, R
SET
= 3.9 k , External reference clock frequency = 10 MHz
with REFCLK Multiplier enabled at 20 ).
Test
Level
AD9856
Typ
Temp
Min
Max
Units
Full
Full
Full
+25°C
+25°C
+25°C
VI
VI
VI
V
V
V
5
5
5
50
3
100
12
10
200
1
50
10
MHz
MHz
MHz
%
pF
MΩ
Bits
mA
%FS
µA
LSB
LSB
pF
dBc/Hz
dBc/Hz
dBc/Hz
V
dBc
dBc
dBc
dBc
dBc
dBc
dBm
%
dB
dBc
dB
+25°C
+25°C
+25°C
+25°C
+25°C
+25°C
+25°C
+25°C
+25°C
+25°C
+25°C
+25°C
+25°C
+25°C
+25°C
+25°C
+25°C
+25°C
+25°C
+25°C
I
I
V
V
V
V
V
V
I
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
V
5
–10
20
+10
10
0.5
1
5
–85
–100
–110
–0.5
70
65
60
55
50
80
50
50
45
1
55
50
±
0.3
2
1.5
MODULATOR CHARACTERISTICS
Adjacent Channel Power (CH Power = –6.98 dBm)
Error Vector Magnitude
I/Q Offset
Inband Spurious Emissions
Pass Band Amplitude Ripple (DC to 80 MHz)
TIMING CHARACTERISTICS
Serial Control Bus
Maximum Frequency
Minimum Clock Pulsewidth High (t
PWH
)
Minimum Clock Pulsewidth Low (t
PWL
)
Maximum Clock Rise/Fall Time
Minimum Data Setup Time (t
DS
)
Minimum Data Hold Time (t
DH
)
Maximum Data Valid Time (t
DV
)
Wake-Up Time
2
Minimum RESET Pulsewidth High (t
RH
)
CMOS LOGIC INPUTS
Logic “1” Voltage
Logic “0” Voltage
Logic “1” Current
Logic “0” Current
Input Capacitance
Full
Full
Full
Full
Full
Full
Full
Full
Full
IV
IV
IV
IV
IV
IV
IV
IV
IV
10
30
30
1
25
0
30
1
5
MHz
ns
ns
ms
ns
ns
ns
ms
REFCLK
Cycles
V
V
µA
µA
pF
+25°C
+25°C
+25°C
+25°C
+25°C
I
I
I
I
V
+2.6
+0.4
12
12
3
–2–
REV. B