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AD9854ASQ 参数 Datasheet PDF下载

AD9854ASQ图片预览
型号: AD9854ASQ
PDF下载: 下载PDF文件 查看货源
内容描述: CMOS 300 MHz的正交完整DDS [CMOS 300 MHz Quadrature Complete-DDS]
分类和应用: 信号电路锁相环或频率合成电路数据分配系统
文件页数/大小: 44 页 / 435 K
品牌: AD [ ANALOG DEVICES ]
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a
FEATURES
300 MHz Internal Clock Rate
Integrated 12-Bit Output DAC
Ultrahigh-Speed, 3 ps RMS Jitter Comparator
Excellent Dynamic Performance: 80 dB SFDR @ 100 MHz
( 1 MHz) A
OUT
4 to 20 Programmable Reference Clock Multiplier
Dual 48-Bit Programmable Frequency Registers
Dual 14-Bit Programmable Phase Offset Registers
12-Bit Amplitude Modulation and Programmable
Shaped On/Off Keying Function
Single Pin FSK and PSK Data Interface
Linear or Nonlinear FM Chirp Functions with Single
Pin Frequency “Hold” Function
Frequency-Ramped FSK
<25 ps RMS Total Jitter in Clock Generator Mode
Automatic Bidirectional Frequency Sweeping
SIN(x)/x Correction
Simplified Control Interface
10 MHz Serial, 2-Wire or 3-Wire SPI-Compatible or
100 MHz Parallel 8-Bit Programming
CMOS 300 MHz Quadrature
Complete-DDS
AD9854
3.3 V Single Supply
Multiple Power-Down Functions
Single-Ended or Differential Input Reference Clock
Small 80-Lead LQFP Packaging
APPLICATIONS
Agile, Quadrature L.O. Frequency Synthesis
Programmable Clock Generator
FM Chirp Source for Radar and Scanning Systems
Test and Measurement Equipment
Commercial and Amateur RF Exciter
GENERAL DESCRIPTION
The AD9854 digital synthesizer is a highly integrated device
that uses advanced DDS technology, coupled with two internal
high-speed, high-performance quadrature D/A converters and a
comparator to form a digitally-programmable I and Q synthesizer
function. When referenced to an accurate clock source, the
AD9854 generates highly stable, frequency-phase-amplitude-
programmable sine and cosine outputs that can be used as an
agile L.O. in communications, radar, and many other applications.
The AD9854’s innovative high-speed DDS core provides 48-bit
frequency resolution (1 microHertz tuning steps). Phase trunca-
tion to 17 bits assures excellent SFDR. The AD9854’s circuit
(continued
on page 14)
FUNCTIONAL BLOCK DIAGRAM
DAC R
SET
300MHz
DIFF/SINGLE
SELECT
FREQUENCY
ACCUMULATOR
PHASE
ACCUMULATOR
DDS
SINE-TO-AMPLITUDE
CONVERTER
INV.
SINC
FILTER
DIGITAL
MULTIPLIERS
I
12-BIT "I"
DAC
ANALOG OUT
REFERENCE
CLOCK IN
4 –20
REF CLK
MULTI-
PLEXER
SYSTEM
CLOCK
Q
PHASE/OFFSET
MODULATION
INV.
SINC
FILTER
RAMP-UP/-DOWN
CLOCK/LOGIC
AND
MULTIPLEXER
MUX
12-BIT
"Q" OR
CONTROL DAC
ANALOG OUT
FSK/BPSK/HOLD
DATA IN
FREQUENCY TUNING WORD/PHASE WORD
MULTIPLEXER AND RAMP START STOP LOGIC
48-BIT
FREQUENCY
TUNING WORD
14-BIT PHASE
OFFSET/
MODULATION
SHAPED
ON/OFF KEYING
12-BIT CONTROL
DAC DATA
ANALOG IN
AD9854
12-BIT
AM
MOD
BIDIRECTIONAL
I/O UPDATE
READ
WRITE
PROGRAMMING REGISTERS
I/O PORT BUFFERS
PROGRAMMABLE RATE
AND UPDATE CLOCKS
COMPARATOR
CLOCK OUT
SERIAL/PARALLEL
SELECT
6-BIT ADDRESS
OR SERIAL
PROGRAMMING
LINES
8-BIT PARALLEL
LOAD
MASTER
RESET
+V
S
GND
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 1999