AD9830
0
–10
–20
–30
10dB/DIV
–40
–50
–60
–70
–80
–90
START 0Hz
RBW 1kHz
VBW 3kHz
STOP 25MHz
ST 50 SEC
Figure 17. f
MCLK
= 50 MHz, f
OUT
= 16.5 MHz, Frequency
Word = 547AE148
Register
FREQ0 REG
Size
32 Bits
Description
Frequency Register 0. This defines
the output frequency, when
FSELECT = 0, as a fraction of the
MCLK frequency.
Frequency Register 1. This de-
fines the output frequency, when
FSELECT = 1, as a fraction of the
MCLK frequency.
Phase Offset Register 0. When
PSEL0 = PSEL1 = 0, the contents
of this register are added to the out-
put of the phase accumulator.
Phase Offset Register 1. When
PSEL0 = 1 and PSEL1 = 0, the
contents of this register are added
to the output of the phase
accumulator.
Phase Offset Register 2. When
PSEL0 = 0 and PSEL1 = 1, the
contents of this register are added
to the output of the phase
accumulator.
Phase Offset Register 3. When
PSEL0 = PSEL1 = 1, the contents
of this register are added to the out-
put of the phase accumulator.
A2
0
0
0
0
1
1
1
1
A1
0
0
1
1
0
0
1
1
A0
0
1
0
1
0
1
0
1
Destination Register
FREQ0 REG 16 LSBs
FREQ0 REG 16 MSBs
FREQ1 REG 16 LSBs
FREQ1 REG 16 MSBs
PHASE0 REG
PHASE1 REG
PHASE2 REG
PHASE3 REG
FREQ1 REG
32 Bits
PHASE0 REG
12 Bits
Figure 19. Addressing the Control Registers
PHASE1 REG
12 Bits
D15
MSB
Figure 20. Frequency Register Bits
D0
LSB
PHASE2 REG
12 Bits
D15 D14 D13 D12 D11
X
X
X
X
MSB
D0
LSB
PHASE3 REG
12 Bits
X = Don't Care
Figure 21. Phase Register Bits
Figure 18. AD9830 Control Registers
REV. A
–9–
AD [ ANALOG DEVICES ]
