(T
MIN
to T
MAX
with AVDD = +5.0 V, DVDD = +5.0 V, DRVDD = +5.0 V, f
ADCCLK
= 6 MHz,
f
CDSCLK1
= 2 MHz, f
CDSCLK2
= 2 MHz, C
L
= 10 pF unless otherwise noted)
Parameter
LOGIC INPUTS
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Input Capacitance
LOGIC OUTPUTS
High Level Output Voltage
Low Level Output Voltage
High Level Output Current
Low Level Output Current
Specifications subject to change without notice.
DIGITAL SPECIFICATIONS
AD9816
Symbol
V
IH
V
IL
I
IH
I
IL
C
IN
V
OH
V
OL
I
OH
I
OL
Min
3.5
1.0
10
10
10
4.5
0.1
50
50
Typ
Max
Units
V
V
µA
µA
pF
V
V
µA
µA
TIMING SPECIFICATIONS
(T
Parameter
MIN
to T
MAX
with DVDD = +5.0 V, DRVDD = +5.0 V)
Symbol
t
CRA
t
CRB
t
ADCLK
t
C1
t
C2
t
C1C2
t
ADC2
t
C2AD
t
C2C1
t
AD
f
SCLK
t
LS
t
LH
t
DS
t
DH
t
RDV
t
OD
t
DV
t
HZ
Min
500
160
80
20
60
5
0
30
10
10
10
10
10
10
10
10
13
15
5
3 (Fixed)
Typ
Max
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ADCCLK Cycles
CLOCK PARAMETERS
3-Channel Conversion Rate
1-Channel Conversion Rate
ADCCLK Pulsewidth
CDSCLK1 Pulsewidth
CDSCLK2 Pulsewidth
CDSCLK1 Falling to CDSCLK2 Rising
ADCCLK Falling to CDSCLK2 Rising
CDSCLK2 Falling to ADCCLK Falling
CDSCLK2 Falling to CDSCLK1 Rising
Aperture Delay for CDS Clocks
SERIAL INTERFACE
Maximum SCLK Frequency
SLOAD to SCLK Set-Up Time
SCLK to SLOAD Hold Time
SDATA to SCLK Rising Set-Up Time
SCLK Rising to SDATA Hold Time
SCLK Falling to SDATA Valid
DATA OUTPUT
Output Delay
3-State to Data Valid
Output Enable High to 3-State
Latency (Pipeline Delay)
2 t
ADCLK
– 30
REV. A
–3–
AD [ ANALOG DEVICES ]
