AD9807/AD9805
127 LSBs and negative 128 LSBs. The offset is variable in
1 LSB increments (see Table V). The contents of the color
pointer in the Configuration Register at the time an Odd or
Even Register is written indicates the color for which that offset
setting applies.
7
6
5
4
3
2
1
0
(after odd/even correction) is the other input. The AD9807/
AD9805 provide a variable word length for the OFFSET data
word. Based on the setting in the Configuration Register, the
OFFSET data word may be 8, 9 or 10 bits wide. The data
format for the OFFSET data bus is straight binary coding. An
all “zeros” data word corresponds to an offset value of 0 LSBs.
An all “ones” data word subtracts an offset value of 256, 512 or
1024 LSBs, depending on the width of OFFSET data word.
The offset is variable in 256, 512 or 1024 increments.
DOUT<n:0>—The
DOUT data bus is bidirectional. CMOS
compatible digital data is available as an output on the DOUT
bus. Data is coded in straight binary format. When CSB and
either WRB or RDB are applied to the AD9807/AD9805, the
DOUT data bus becomes an input/output port for the register
data, shown as MPU<7:0>. The timing and latency for the
DOUT data bus are given in Figures 11 through 15.
FUNCTIONAL OVERVIEW
O/E OFFSET (LSB)
O/E OFFSET
O/E OFFSET
O/E OFFSET
O/E OFFSET
O/E OFFSET
O/E OFFSET
O/E OFFSET (MSB)
Figure 10. Odd and Even Offset Registers Format
Table V. Odd/Even Offset Register Coding
Odd/Even Register Contents
0111 1111
.
.
.
0000 0001
0000 0000
1111 1111
.
.
.
1000 0000
DATA BUSES
Offset Value
+127 LSB
.
.
.
+1 LSB
0 LSB
–1 LSB
.
.
.
–128 LSB
It is possible to operate the AD9807/AD9805 in one of five
modes: 3-Channel Operation with CDS, 3-Channel SHA
Operation, 1-Channel Operation with CDS, 1-Channel SHA
Operation and 2-Channel Bayer Mode. A description of each of
the five modes follows.
3-Channel Operation with CDS
GAIN<n:0>—The
GAIN data bus gives the user access to the
internal digital multiplier. Data from the GAIN bus is latched
into the appropriate internal registers in accordance with the
timing shown in Figure 1. Note that the GAIN data must be
valid on the rising edges of ADCCLK. The contents of the
register become one multiplicand of the digital multiplier; the
output data from the digital subtracter is the other multiplicand.
The AD9807/AD9805 provide a variable word length for the
GAIN data word. Based on the setting in the Configuration
Register, the GAIN data word may be 10, 11 or 12 bits wide
(8, 9 or 10 bits wide for the AD9805). The data format for the
GAIN data bus is straight binary coding. An all “zeros” data
word always corresponds to a gain setting of 1×. An all “ones”
data word corresponds to a gain setting dependent on Bits 0–2
of the Configuration Register. The gain is variable in 1024,
2048, or 4096 (256, 512 or 1024 for the AD9805) increments
depending on the width of GAIN data word.
OFFSET<m:0>
The OFFSET data bus gives the user access to the internal
digital subtracter. Data from the OFFSET bus is latched into
the appropriate internal registers in accordance with the timing
shown in Figure 1. Note that the OFFSET data must be valid
on the rising edges of ADCCLK. The contents of the register
become the subtrahend; the output data from the A/D converter
REV. 0
This mode of the AD9807/AD9805 enables simultaneous
sampling of a triple output CCD. The CCD waveforms are ac
coupled to the VINR, VING and VINB pins of the AD9807/
AD9805 where they are automatically biased at an appropriate
voltage level using the on-chip clamp; the inputs may alterna-
tively be dc coupled if they have already been appropriately level
shifted. The internal CDSs take two samples of the incoming
pixel data: the first samples (CDSCLK1) are taken during the
reset time while the second samples (CDSCLK2) are taken
during the video, or data, portion of the input pixels. The offsets
of the three input channels are modified by the values stored in
the input offset registers. The voltage differences of the reset
levels and video levels are inverted and amplified by the PGAs;
the settings in the corresponding PGA Gain Registers determine
the gains of the PGAs. These outputs from the PGAs are then
routed through a high speed multiplexer to a 12-bit A/D
converter (10-bit for AD9805) for digitization; the multiplexer
cycles between the red, green and then blue channels. After
digitization, the data is modified by the amount indicated in the
Odd and Even Offset Registers. A digital subtracter allows
additional pixel rate offset modification of each color based on
the values written to the OFFSET data bus. Finally, a digital
multiplier allows pixel rate gain modification of each color based
on the values written to the GAIN data bus. Latency for the red,
green and blue channels is 6 ADCCLK cycles (9 cycles for the
gain and offset bus; see Figure 12).
The STRTLN signal indicates the first red, green and blue
pixels in a scan line, and the red channel is always the first pixel
digitized. The state of STRTLN is evaluated on the rising
edges of ADCCLK. When STRTLN is low, the internal
circuitry is reset on the next rising edge of ADCCLK; the
multiplexer is switched to the red channel and the odd/even
circuitry is configured to expect even pixels. After STRTLN
goes high, the first set of pixels is assumed to be even. Consecu-
tive sets of pixels (red, green and blue) are assumed to alternate
between odd and even pixel sets.
–13–
AD [ ANALOG DEVICES ]
