AD9807/AD9805
ANALOG
INPUTS
t
AD
R0, G0, B0
R1, G1, B1
Rn, Gn, Bn
t
AD
STRTLN
t
C1A
CDSCLK1
t
C1C2A
t
C2C1A
t
CRA
t
S
t
H
t
C1AD
CDSCLK2
t
C2A
t
ACLK
t
ACLK
ADCCLK
R
G
B
t
STL1
R
G
B
R
G
B
t
CP2
GAIN<n:0>
OFFSET<m:0>
R0
G0
B0
R1
G1
B1
t
GOS
t
GOH
Figure 1a. 3-Channel CDS-Mode Clock Timing
ANALOG
INPUTS
R0, G0, B0
(0V)
R1, G1, B1
Rn, Gn, Bn
t
AD
STRTLN
t
C2A
CDSCLK1
t
CRA
t
S
t
H
t
ACLK
t
ACLK
ADCCLK
t
STL1
t
CP
GAIN<n:0>
OFFSET<m:0>
t
GOS
t
GOH
Figure 1b. 3-Channel SHA-Mode Clock Timing
ANALOG
INPUTS
t
AD
PIXEL 0
PIXEL 1
PIXEL n
t
AD
STRTLN
t
C1B
CDSCLK1
t
C1C2B
t
C2C1B
t
CRB
t
S
t
H
t
C2B
CDSCLK2
t
ACLK
ADCCLK
t
ACLK
t
STL2
t
CP
GAIN<n:0>
OFFSET<m:0>
G0
G1
G2
t
GOS
t
GOH
Figure 1c. 1-Channel CDS-Mode Clock Timing (for B and G Only)
–8–
REV. 0