AD9772A
RED
TP16
BLK
TP17
WHT
TP5
WHT
TP6
AVDD
3
C5
0.1ꢂF
EXT REF
B
R10
1.91kꢁ
REFLO
JP4
C4
0.1ꢂF
2
C6
1ꢂF
A
AVDD
INT REF
1
DVDD
RED
TP14
R6
50ꢁ
NOTE:
SHIELD AROUND R5, C1
CONNECTED TO PLLVDD
C7
0.1ꢂF
C8
0.1ꢂF
48 47 46 45 44 43 42 41 40 39 38 37
TP11
SLEEP WHT
C1
VAL
1
2
36
R5
TP15
BLK
PIN 1
IDENTIFIER
VAL
35
34
33
32
31
30
29
28
27
26
25
LPF
3
MSB DB13
DB12
DB11
DB10
DB9
PLLVDD
4
5
CLKVDD
U1
C9
1ꢂF
C10
0.1ꢂF
6
CLK–
CLK+
DIV0
DIV1
7
c
AD9772A
8
DB8
9
DB7
10
11
CLKVDD
DB6
RESET
DB5
12
PLL-LOCK
DB4
3
B
13 14 15 16 17 18 19 20 21 22 23 24
TP10
WHT
JP5
c
2
A
1
3
1
J1
1
2
B
A
TP7 RED
C11
0.1ꢂF
TP3
WHT
c
c
JP6
2
TP28
WHT
3
1
CONNECT GNDs AS SHOWN UNDER
USING BOTTOM SIGNAL LAYER
B
A
TP4
WHT
JP7
C12
1ꢂF
2
MOD0
DVDD
3
c
TP1
WHT
3
1
WHT
TP12 CLOCK
B
B
H
L
H
L
J3
1
JP11
JP10
2
2
DVDD
A
A
MOD1
1
3
2
c
TP2
WHT
B
DGND
SE
JP1
DF
JP2
2
NOTE:
A
DF
LOCATE ALL DECOUPLING CAPS (C5 – C12) AS CLOSE AS POSSIBLE TO DUT,
PREFERABLY UNDER DUT ON BOTTOM SIGNAL LAYER.
JP8
EDGE
1
CLKVDD
T1
R2
1kꢁ
1
CLOCK
S
R16
VAL
P
6
3
1
2
3
C3
R8
B
A
R3
1kꢁ
C19
0.1ꢂF
SE
DF
T2
JP3
10pF 50ꢁ
4
2
IA
IB
3
S
c
J6
c
1
P
IOUT
4
6
R9
OPT
2
2
1
3
R1
50ꢁ
B
A
DF
SE
C2
R7
JP9
2
R17
VAL
10pF 50ꢁ
1
c
Figure 38. Drafting Schematic of Evaluation Board (continued)
–26–
REV. A
ADI [ ADI ]
