Data Sheet
AD9763/AD9765/AD9767
C
500Ω
OPT
I
OUTA
225Ω
225Ω
AD9763/
AD9765/
AD9767
R
200Ω
FB
AD8055
I
= 10mA
OUTFS
I
OUTB
C
OPT
I
OUTA
1kΩ
AVDD
U1
AD9763/
AD9765/
AD9767
V
= I
OUTFS
× R
FB
OUT
25Ω
25Ω
500Ω
200Ω
I
OUTB
Figure 74. Single-Supply DC Differential-Coupled Circuit
Figure 76. Unipolar Buffered Voltage Output
SINGLE-ENDED, UNBUFFERED VOLTAGE OUTPUT
POWER AND GROUNDING CONSIDERATIONS
Power Supply Rejection
Figure 75 shows the AD9763/AD9765/AD9767 configured to
provide a unipolar output range of approximately 0 V to 0.5 V
for a doubly terminated 50 ꢀ cable, because the nominal full-
scale current (IOUTFS) of 20 mA flows through the equivalent
Many applications seek high speed and high performance under
less than ideal operating conditions. In these applications, the
implementation and construction of the printed circuit board is
as important as the circuit design. Proper RF techniques must
be used for device selection, placement, and routing as well as
power supply bypassing and grounding to ensure optimum
performance. Figure 92 to Figure 93 illustrate recommended
printed circuit board ground, power, and signal plane layouts
that are implemented on the AD9763/AD9765/AD9767
evaluation board.
R
LOAD of 25 ꢀ. In this case, RLOAD represents the equivalent load
resistance seen by IOUTA or IOUTB. The unused output (IOUTA or IOUTB
can be connected directly to ACOM or via a matching RLOAD
)
.
Different values of IOUTFS and RLOAD can be selected as long as the
positive compliance range is adhered to. One additional
consideration in this mode is the INL (see the Analog Outputs
section). For optimum INL performance, the single-ended,
buffered voltage output configuration is suggested.
I
= 20mA
OUTFS
V
= 0V TO 0.5V
OUTA
One factor that can measurably affect system performance is
the ability of the DAC output to reject dc variations or ac noise
superimposed on the analog or digital dc power distribution.
This is referred to as the power supply rejection ratio (PSRR).
For dc variations of the power supply, the resulting performance
of the DAC directly corresponds to a gain error associated with
the DAC’s full-scale current, IOUTFS. AC noise on the dc supplies
is common in applications where the power distribution is
generated by a switching power supply. Typically, switching
power supply noise occurs over the spectrum of tens of
kilohertz to several megahertz. The PSRR vs. frequency of the
AD9763/AD9765/AD9767 AVDD supply over this frequency
range is shown in Figure 77.
I
OUTA
AD9763/
AD9765/
AD9767
50Ω
50Ω
I
OUTB
25Ω
Figure 75. 0 V to 0.5 V Unbuffered Voltage Output
SINGLE-ENDED, BUFFERED VOLTAGE OUTPUT
CONFIGURATION
Figure 76 shows a buffered single-ended output configuration
in which the U1 op amp performs an I-V conversion on the
AD9763/AD9765/AD9767 output current. U1 maintains IOUTA
(or IOUTB) at a virtual ground, thus minimizing the nonlinear
output impedance effect on the INL performance of the DAC,
90
as described in the Analog Outputs section. Although this single-
ended configuration typically provides the best dc linearity
performance, its ac distortion performance at higher DAC update
rates may be limited by the slewing capabilities of U1. U1
provides a negative unipolar output voltage, and its full-scale
output voltage is simply the product of RFB and IOUTFS. Set the
full-scale output within U1’s voltage output swing capabilities
by scaling IOUTFS and/or RFB. An improvement in ac distortion
performance may result with a reduced IOUTFS because the signal
current U1 has to sink will be subsequently reduced.
85
80
75
70
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1.1
FREQUENCY (MHz)
Figure 77. AVDD Power Supply Rejection Ratio vs. Frequency
Rev. G | Page 29 of 44
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