+5V
0.1 F
OPTIONAL
EXTERNAL
REF BUFFER
REFLO
+1.2V REF
REFIO
50pF
COMP1
AVDD
ADDITIONAL
LOAD
0.1 F
2k
FS ADJ
CURRENT
SOURCE
ARRAY
The small signal bandwidth of the reference control amplifier is
approximately 1.8 MHz and can be reduced by connecting an
external capacitor between COMP1 and AVDD. The output of
the control amplifier, COMP1, is internally compensated via a
50 pF capacitor that limits the control amplifier small-signal
bandwidth and reduces its output impedance. Any additional
external capacitance further limits the bandwidth and acts as
a filter to reduce the noise contribution from the reference
amplifier. If I
REF
is fixed for an application, a 0.1
µF
ceramic chip
capacitor is recommended.
I
REF
can be varied for a fixed R
SET
by disabling the internal
reference and varying the common-mode voltage over its
compliance range of 1.25 V to 0.10 V. REFIO can be driven by
a single-supply amplifier or DAC, thus allowing I
REF
to be var-
ied for a fixed R
SET
. Since the input impedance of REFIO is
approximately 1 MΩ, a simple R-2R ladder DAC configured in
the voltage mode topology may be used to control the gain. This
circuit is shown in Figure 15 using the AD7524 and an external
1.2 V reference, the AD1580. Note another AD9708 could also
be used as the gain control DAC since it can also provide a
programmable unipolar output up to 1.2 V.
ANALOG OUTPUTS AND OUTPUT CONFIGURATIONS
Figure 13. Internal Reference Configuration
The internal reference can be disabled by connecting REFLO to
AVDD. In this case, an external reference may then be applied
to REFIO as shown in Figure 14. The external reference may
provide either a fixed reference voltage to enhance accuracy and
drift performance or a varying reference voltage for gain control.
Note that the 0.1
µF
compensation capacitor is not required
since the internal reference is disabled, and the high input
impedance (i.e., 1 MΩ) of REFIO minimizes any loading of the
external reference.
AVDD
0.1 F
AVDD
V
REFIO
REFLO
+1.2V REF
50pF
REFIO
FS ADJ
R
SET
I
REF
=
V
REFIO
/R
SET
COMP1
AVDD
EXTERNAL
REF
CURRENT
SOURCE
ARRAY
REFERENCE
CONTROL
AMPLIFIER
Figure 14. External Reference Configuration
The AD9708 also contains an internal control amplifier that is
used to regulate the DAC’s full-scale output current, I
OUTFS
.
The control amplifier is configured as a V-I converter, as shown
in Figure 14, such that its current output, I
REF
, is determined by
the ratio of the V
REFIO
and an external resistor, R
SET
, as stated
in Equation 4. The control amplifier allows a wide (10:1)
adjustment span of I
OUTFS
over a 2 mA to 20 mA range by setting
I
REF
between 62.5
µA
and 625
µA.
The wide adjustment span of
I
OUTFS
provides several application benefits. The first benefit
relates directly to the power dissipation of the AD9708, which is
proportional to I
OUTFS
(refer to the POWER DISSIPATION
section). The second benefit relates to the 20 dB adjustment,
which is useful for system gain control purposes.
The AD9708 produces two complementary current outputs,
I
OUTA
and I
OUTB
, which may be converted into complementary
single-ended voltage outputs, V
OUTA
and V
OUTB
, via a load resistor,
R
LOAD
, as described in the DAC TRANSFER FUNCTION
section. Figure 16 shows the AD9708 configured to provide a
positive unipolar output range of approximately 0 V to +0.5 V
for a double terminated 50
Ω
cable for a nominal full-scale
current, I
OUTFS
, of 20 mA. In this case, R
LOAD
represents the
equivalent load resistance seen by IOUTA or IOUTB and is
equal to 25
Ω.
The unused output (IOUTA or IOUTB) can be
connected to ACOM directly or via a matching R
LOAD
. Different
values of I
OUTFS
and R
LOAD
can be selected as long as the posi-
tive compliance range is adhered to.
IOUTA
22
50
IOUTB
21
25
I
OUTFS
= 20mA
V
OUTA
= 0 TO +0.5V
50
Figure 16. 0 V to +0.5 V Unbuffered Voltage Output
Alternatively, an amplifier could be configured as an I-V converter
thus converting IOUTA or IOUTB into a negative unipolar
AVDD
OPTIONAL
BANDLIMITING
CAPACITOR
REFLO
COMP1
50pF
CURRENT
SOURCE
ARRAY
AVDD
AVDD
R
FB
1.2V
OUT1
OUT2
AGND
V
DD
V
REF
0.1V TO 1.2V
+1.2V REF
REFIO
FS ADJ
R
SET
I
REF
=
V
REF
/R
SET
AD7524
AD1580
DB7–DB0
Figure 15. Single-Supply Gain Control Circuit
–8–
REV. B
AD [ ANALOG DEVICES ]
