AD9650
THEORY OF OPERATION
The AD9650 dual-core analog-to-digital converter (ADC) is
used for digitizing high frequency, wide dynamic range signals with
input frequencies of up to 300 MHz. The user can sample any f
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frequency segment from dc to 300 MHz using appropriate low-
pass or band-pass filtering at the ADC inputs with little loss in
ADC performance. The ADCs can also be operated with
independent analog inputs.
In quadrature applications, the AD9650 can be used as a baseband
or direct down-conversion receiver, in which one ADC is used
for I input data, and the other is used for Q input data.
Synchronization capability is provided to allow synchronized
timing between multiple devices.
Programming and control of the AD9650 are accomplished
using a 3-wire, SPI-compatible serial interface.
A small resistor in series with each input can help reduce the
peak transient current required from the output stage of the
driving source. A shunt capacitor can be placed across the inputs
to provide dynamic charging currents. This passive network
creates a low-pass filter at the ADC input; therefore, the precise
values are dependent on the application.
In intermediate frequency (IF) undersampling applications, any
shunt capacitors should be reduced. In combination with the
driving source impedance, the shunt capacitors limit the input
bandwidth. Refer to the
Application Note,
Frequency
Domain Response of Switched-Capacitor ADCs;
the
Application Note,
A Resonant Approach to Interfacing Amplifiers to
Switched-Capacitor ADCs;
and the
Analog Dialogue
article,
for more information on this subject (visit
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ADC ARCHITECTURE
The AD9650 architecture consists of a dual front-end sample-
and-hold circuit, followed by a pipelined, switched-capacitor
ADC. The quantized outputs from each stage are combined into
a final 16-bit result in the digital correction logic. The pipelined
architecture permits the first stage to operate on a new input
sample and the remaining stages to operate on the preceding
samples. Sampling occurs on the rising edge of the clock.
Each stage of the pipeline, excluding the last, consists of a low
resolution flash ADC connected to a switched-capacitor digital-
to-analog converter (DAC) and an interstage residue amplifier
(MDAC). The MDAC magnifies the difference between the
reconstructed DAC output and the flash input for the next stage
in the pipeline. One bit of redundancy is used in each stage to
facilitate digital correction of flash errors. The last stage simply
consists of a flash ADC.
The input stage of each channel contains a differential sampling
circuit that can be ac- or dc-coupled in differential or single-
ended modes. The output staging block aligns the data, corrects
errors, and passes the data to the output buffers. The output buffers
are powered from a separate supply, allowing digital output noise to
be separated from the analog core. During power-down, the output
buffers go into a high impedance state.
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Figure 77. Switched-Capacitor Input
For best dynamic performance, the source impedances driving
VIN+x and VIN−x should be matched, and the inputs should
be differentially balanced.
An internal differential reference buffer creates positive and
negative reference voltages that define the input span of the ADC
core. The span of the ADC core is set by this buffer to 2 × VREF.
Input Common Mode
The analog inputs of the AD9650 are not internally dc biased.
In ac-coupled applications, the user must provide this bias exter-
nally. Setting the device so that VCM = 0.5 × AVDD (or 0.9 V) is
recommended for optimum performance, but the device
functions over a wider range with reasonable performance
(see Figure 67). An on-chip, common-mode voltage reference
is included in the design and is available from the VCM pin.
Optimum performance is achieved when the common-mode
voltage of the analog input is set by the VCM pin voltage
(typically 0.5 × AVDD). The VCM pin must be decoupled to
ground by a 0.1 μF capacitor, as described in the Applications
ANALOG INPUT CONSIDERATIONS
The analog input to the AD9650 is a differential switched-
capacitor circuit that has been designed for optimum performance
while processing a differential input signal.
The clock signal alternatively switches the input between sample
mode and hold mode (see Figure 77). When the input is switched
into sample mode, the signal source must be capable of charging
the sample capacitors and settling within �½ of a clock cycle.
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