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AD9220ARS 参数 Datasheet PDF下载

AD9220ARS图片预览
型号: AD9220ARS
PDF下载: 下载PDF文件 查看货源
内容描述: 完整的12位1.5 / 3.0 / 10.0 MSPS单片A / D转换器 [Complete 12-Bit 1.5/3.0/10.0 MSPS Monolithic A/D Converters]
分类和应用: 转换器
文件页数/大小: 28 页 / 353 K
品牌: ADI [ ADI ]
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AD9221/AD9223/AD9220  
The addition of a differential input structure gives the user an  
additional level of flexibility that is not possible with traditional  
flash converters. The input stage allows the user to easily con-  
figure the inputs for either single-ended operation or differential  
operation. The A/D’s input structure allows the dc offset of the  
input signal to be varied independently of the input span of the  
converter. Specifically, the input to the A/D core is the differ-  
ence of the voltages applied at the VINA and VINB input pins.  
Therefore, the equation,  
The SHA’s optimum distortion performance for a differential or  
single-ended input is achieved under the following two condi-  
tions: (1) the common-mode voltage is centered around mid  
supply (i.e., AVDD/2 or approximately 2.5 V) and (2) the input  
signal voltage span of the SHA is set at its lowest (i.e., 2 V input  
span). This is due to the sampling switches, QS1, being CMOS  
switches whose RON resistance is very low but has some signal  
dependency which causes frequency dependent ac distortion  
while the SHA is in the track mode. The RON resistance of a  
CMOS switch is typically lowest at its midsupply but increases  
symmetrically as the input signal approaches either AVDD or  
AVSS. A lower input signal voltage span centered at midsupply  
reduces the degree of RON modulation.  
VCORE = VINA – VINB  
(1)  
defines the output of the differential input stage and provides  
the input to the A/D core.  
The voltage, VCORE, must satisfy the condition,  
Figure 32a compares the AD9221/AD9223/AD9220’s THD vs.  
frequency performance for a 2 V input span with a common-  
mode voltage of 1 V and 2.5 V. Note how each A/D with a  
common-mode voltage of 1 V exhibits a similar degradation in  
THD performance at higher frequencies (i.e., beyond 750 kHz).  
Similarly, note how the THD performance at lower frequencies  
becomes less sensitive to the common-mode voltage. As the  
input frequency approaches dc, the distortion will be domi-  
nated by static nonlinearities such as INL and DNL. It is  
important to note that these dc static nonlinearities are inde-  
pendent of any RON modulation.  
VREF VCORE VREF  
(2)  
where VREF is the voltage at the VREF pin.  
While an infinite combination of VINA and VINB inputs exist  
that satisfy Equation 2, there is an additional limitation placed  
on the inputs by the power supply voltages of the AD9221/  
AD9223/AD9220. The power supplies bound the valid operat-  
ing range for VINA and VINB. The condition,  
AVSS – 0.3 V < VINA < AVDD + 0.3 V  
AVSS – 0.3 V < VINB < AVDD + 0.3 V  
(3)  
where AVSS is nominally 0 V and AVDD is nominally +5 V,  
defines this requirement. Thus, the range of valid inputs for  
VINA and VINB is any combination that satisfies both Equa-  
tions 2 and 3.  
–50  
AD9220  
1V  
CM  
–60  
For additional information showing the relationship between  
VINA, VINB, VREF and the digital output of the AD9221/  
AD9223/AD9220, see Table IV.  
AD9223  
1V  
AD9221  
CM  
CM  
1V  
–70  
–80  
–90  
Refer to Table I and Table II at the end of this section for a  
summary of both the various analog input and reference  
configurations.  
AD9223  
2.5V  
CM  
AD9220  
ANALOG INPUT OPERATION  
AD9221  
2.5V  
2.5V  
CM  
CM  
Figure 32 shows the equivalent analog input of the AD9221/  
AD9223/AD9220 which consists of a differential sample-and-  
hold amplifier (SHA). The differential input structure of the  
SHA is highly flexible, allowing the devices to be easily config-  
ured for either a differential or single-ended input. The dc  
offset, or common-mode voltage, of the input(s) can be set to  
accommodate either single-supply or dual supply systems. Also,  
note that the analog inputs, VINA and VINB, are interchange-  
able with the exception that reversing the inputs to the VINA  
and VINB pins results in a polarity inversion.  
0.1  
1
10  
FREQUENCY – MHz  
Figure 32a. AD9221/AD9223/AD9220 THD vs. Frequency for  
CM = 2.5 V and 1.0 V (AIN = –0.5 dB, Input Span = 2.0 V p-p)  
V
Due to the high degree of symmetry within the SHA topology, a  
significant improvement in distortion performance for differen-  
tial input signals with frequencies up to and beyond Nyquist can  
be realized. This inherent symmetry provides excellent cancella-  
tion of both common-mode distortion and noise. Also, the  
required input signal voltage span is reduced by a half which  
further reduces the degree of RON modulation and its effects on  
distortion.  
C
H
Q
S2  
+
C
C
PIN  
PAR  
C
Q
S
S1  
The optimum noise and dc linearity performance for either differ-  
ential or single-ended inputs is achieved with the largest input  
signal voltage span (i.e., 5 V input span) and matched input  
impedance for VINA and VINB. Note that only a slight degra-  
dation in dc linearity performance exists between the 2 V and  
5 V input span as specified in the AD9221/AD9223/AD9220  
DC SPECIFICATIONS.  
VINA  
VINB  
Q
C
Q
H1  
S
S1  
C
C
PIN  
PAR  
Q
S2  
C
H
Figure 32. AD9221/AD9223/AD9220 Simplified Input Circuit  
–10–  
REV. D