AD8605/AD8606/AD8608
OUTLINE DIMENSIONS
0.50 REF
SEATING
0.94
0.90
0.86
0.37
0.36
0.35
PLANE
2
1
0.87
A
B
C
0.23
0.18
0.14
BALL 1
IDENTIFIER
1.33
0.50
1.29
1.25
0.21
0.17
0.14
0.12
TOP VIEW
(BALL SIDE DOWN)
0.20
0.50
BOTTOM VIEW
(BALL SIDE UP)
Figure 57. 5-Ball Wafer Level Chip Scale Package [WLCSP]
(CB-5-1)
Dimensions shown in millimeters
2.90 BSC
5
1
4
3
2.80 BSC
1.60 BSC
2
PIN 1
0.95 BSC
1.90
BSC
1.30
1.15
0.90
1.45 MAX
0.22
0.08
10°
5°
0°
0.15 MAX
0.50
0.30
0.60
0.45
0.30
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MO-178-AA
Figure 58. 5-Lead Small Outline Transistor Package [SOT-23]
(RJ-5)
Dimensions shown in millimeters
3.20
3.00
2.80
8
1
5
4
5.15
4.90
4.65
3.20
3.00
2.80
PIN 1
0.65 BSC
0.95
0.85
0.75
1.10 MAX
0.80
0.60
0.40
8°
0°
0.15
0.00
0.38
0.22
0.23
0.08
SEATING
PLANE
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-187-AA
Figure 59. 8-Lead Mini Small Outline Package [MSOP]
(RM-8)
Dimensions shown in millimeters
Rev. H | Page 20 of 24
ADI [ ADI ]
