AD8551/AD8552/AD8554
earn the reputation of being among the most precise amplifiers
available on the market.
Other potential sources of offset error are thermoelectric
voltages on the circuit board. This voltage, also called Seebeck
voltage, occurs at the junction of two dissimilar metals and is
proportional to the temperature of the junction. The most
common metallic junctions on a circuit board are solder-to-
board trace and solder-to-component lead. Figure 54 shows a
cross-section of the thermal voltage error sources. If the
temperature of the PC board at one end of the component (TA1)
is different from the temperature at the other end (TA2), the
resulting Seebeck voltages are not equal, resulting in a thermal
voltage error.
HIGH GAIN, CMRR, PSRR
Common-mode and power supply rejection are indications
of the amount of offset voltage an amplifier has as a result of a
change in its input common-mode or power supply voltages. As
shown in the previous section, the autocorrection architecture
of the AD855x allows it to quite effectively minimize offset volt-
ages. The technique also corrects for offset errors caused by
common-mode voltage swings and power supply variations.
This results in superb CMRR and PSRR figures in excess of
130 dB. Because the autocorrection occurs continuously, these
figures can be maintained across the entire temperature range
of the device, from −40°C to +125°C.
This thermocouple error can be reduced by using dummy
components to match the thermoelectric error source. Placing
the dummy component as close as possible to its partner ensures
both Seebeck voltages are equal, thus canceling the thermo-
couple error. Maintaining a constant ambient temperature on
the circuit board further reduces this error. The use of a ground
plane helps distribute heat throughout the board and reduces
EMI noise pickup.
MAXIMIZING PERFORMANCE THROUGH
PROPER LAYOUT
To achieve the maximum performance of the extremely high
input impedance and low offset voltage of the AD855x, care is
needed in laying out the circuit board. The PC board surface
must remain clean and free of moisture to avoid leakage cur-
rents between adjacent traces. Surface coating of the circuit
board reduces surface moisture and provides a humidity barrier,
reducing parasitic resistance on the board. The use of guard
rings around the amplifier inputs further reduces leakage cur-
rents. Figure 52 shows proper guard ring configuration, and
Figure 53 shows the top view of a surface-mount layout. The
guard ring does not need to be a specific width, but it should
form a continuous loop around both inputs. By setting the
guard ring voltage equal to the voltage at the noninverting
input, parasitic capacitance is minimized as well. For further
reduction of leakage currents, components can be mounted to
the PC board using Teflon standoff insulators.
COMPONENT
LEAD
V
V
SC2
SOLDER
SC1
+
SURFACE-MOUNT
COMPONENT
+
+
V
V
TS1
TS2
+
PC BOARD
T
T
A2
A1
IF T ≠ T , THEN
COPPER
TRACE
A1
+ V
A2
V
≠ V
TS2
+ V
SC2
TS1
SC1
Figure 54. Mismatch in Seebeck Voltages Causes
Thermoelectric Voltage Error
R
F
R
1
V
OUT
V
IN
AD8551/
AD8552/
AD8554
R
= R
1
S
A
= 1 + (R /R )
F 1
V
V
OUT
V
OUT
V
NOTES
1. R SHOULD BE PLACED IN CLOSE PROXIMITY AND
V
IN
IN
AD8552
AD8552
S
ALIGNMENT TO R TO BALANCE SEEBECK VOLTAGES.
1
Figure 55. Using Dummy Components to Cancel
Thermoelectric Voltage Errors
V
IN
V
OUT
1/f NOISE CHARACTERISTICS
AD8552
Another advantage of auto-zero amplifiers is their ability to
cancel flicker noise. Flicker noise, also known as 1/f noise, is
noise inherent in the physics of semiconductor devices, and it
increases 3 dB for every octave decrease in frequency. The 1/f
corner frequency of an amplifier is the frequency at which the
flicker noise is equal to the broadband noise of the amplifier.
At lower frequencies, flicker noise dominates, causing higher
degrees of error for sub-Hertz frequencies or dc precision
applications.
Figure 52. Guard Ring Layout and Connections to Reduce
PC Board Leakage Currents
V+
R
R
2
1
AD8552
R
R
1
2
V
IN1
V
IN2
GUARD
RING
V
GUARD
RING
REF
V
REF
V–
Figure 53. Top View of AD8552 SOIC Layout with Guard Rings
Rev. C | Page 16 of 24
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