AD847
+V
O FFSET NULLING
S
T he input offset voltage of the AD847 is very low for a high
speed op amp, but if additional nulling is required, the circuit
shown in Figure 21 can be used.
C
F
OUTPUT
–IN
+IN
–V
S
Figure 21. Offset Nulling
NULL 1
NULL 8
INP UT CO NSID ERATIO NS
An input resistor (RIN in Figure 20) is required in circuits where
the input to the AD847 will be subjected to transient or con-
tinuous overload voltages exceeding the ±6 V maximum differ-
ential limit. T his resistor provides protection for the input
transistors by limiting the maximum current that can be forced
into their bases.
Figure 22. AD847 Sim plified Schem atic
GRO UND ING AND BYP ASSING
In designing practical circuits with the AD847, the user must
remember that whenever high frequencies are involved, some
special precautions are in order. Circuits must be built with
short interconnect leads. A large ground plane should be used
whenever possible to provide a low resistance, low inductance
circuit path, as well as minimizing the effects of high frequency
coupling. Sockets should be avoided because the increased
interlead capacitance can degrade bandwidth.
For high performance circuits it is recommended that a resistor
(RB in Figures 19 and 20) be used to reduce bias current errors
by matching the impedance at each input. T he offset voltage er-
ror will be reduced by more than an order of magnitude.
TH EO RY O F O P ERATIO N
Feedback resistors should be of low enough value to assure that
the time constant formed with the capacitance at the amplifier
summing junction will not limit the amplifier performance.
Resistor values of less than 5 kΩ are recommended. If a larger
resistor must be used, a small (<10 pF) feedback capacitor in
parallel with the feedback resistor, RF, may be used to compen-
sate for the input capacitances and optimize the dynamic perfor-
mance of the amplifier.
T he AD847 is fabricated on Analog Devices’ proprietary
complementary bipolar (CB) process which enables the con-
struction of pnp and npn transistors with similar fT s in the
600 MHz to 800 MHz region. T he AD847 circuit (Figure 22)
includes an npn input stage followed by fast pnps in the folded
cascode intermediate gain stage. T he CB pnps are also used in
the current amplifying output stage. T he internal compensation
capacitance that makes the AD847 unity gain stable is provided
by the junction capacitances of transistors in the gain stage.
Power supply leads should be bypassed to ground as close as
possible to the amplifier pins. Ceramic disc capacitors of
0.1 µF are recommended.
T he capacitor, CF, in the output stage mitigates the effect of ca-
pacitive loads. At low frequencies and with low capacitive
loads, the gain from the compensation node to the output is
very close to unity. In this case CF is bootstrapped and does not
contribute to the compensation capacitance of the part. As the
capacitive load is increased, a pole is formed with the output
impedance of the output stage. T his reduces the gain, and
therefore, CF is incompletely bootstrapped. Some fraction of CF
contributes to the compensation capacitance, and the unity gain
bandwidth falls. As the load capacitance is increased, the band-
width continues to fall, and the amplifier remains stable.
REV. F
–9–
ADI [ ADI ]
