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AD844AN 参数 Datasheet PDF下载

AD844AN图片预览
型号: AD844AN
PDF下载: 下载PDF文件 查看货源
内容描述: 60兆赫, 2000 V / us的单片运算放大器 [60 MHz, 2000 V/us Monolithic Op Amp]
分类和应用: 运算放大器光电二极管
文件页数/大小: 12 页 / 494 K
品牌: AD [ ANALOG DEVICES ]
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AD844
Response as an I-V Converter
The AD844 works well as the active element in an operational
current to voltage converter, used in conjunction with an exter-
nal scaling resistor, R1, in Figure 27. This analysis includes the
stray capacitance, C
S
, of the current source, which might be a
high speed DAC. Using a conventional op amp, this capaci-
tance forms a “nuisance pole” with R1 which destabilizes the
closed loop response of the system. Most op amps are inter-
nally compensated for the fastest response at unity gain, so the
pole due to R1 and C
S
reduces the already narrow phase margin
of the system. For example, if R1 were 2.5 kΩ a C
S
of 15 pF
would place this pole at a frequency of about 4 MHz, well
within the response range of even a medium speed operational
amplifier. In a current feedback amp this nuisance pole is no
longer determined by R1 but by the input resistance, R
IN
. Since
this is about 50
for the AD844, the same 15 pF forms a pole
212 MHz and causes little trouble. It can be shown that the
response of this system is:
V
OUT
=
Isig
K R1
(1
+
sTd
)(1
+
sTn
)
age, ensured by the close matching of like polarity transistors
operating under essentially identical bias conditions. Laser trim-
ming nulls the residual offset voltage, down to a few tens of mi-
crovolts. The inverting input is the common emitter node of a
complementary pair of grounded base stages and behaves as a
current summing node. In an ideal current feedback op amp the
input resistance would be zero. In the AD844 it is about 50
Ω.
where K is a factor very close to unity and represents the finite
dc gain of the amplifier, Td is the dominant pole and Tn is the
nuisance pole:
K
=
Rt
Rt
+
R1
(assuming
R
IN
<<
R1)
Figure 28. Simplified Schematic
Td
=
KR1Ct
Tn
= R
IN
C
S
Using typical values of R1 = 1 kΩ and Rt = 3 MΩ, K is 0.9997;
in other words, the “gain error” is only 0.03%. This is much
less than the scaling error of virtually all DACs and can be
absorbed, if necessary, by the trim needed in a precise system.
In the AD844, Rt is fairly stable with temperature and supply
voltages, and consequently the effect of finite “gain” is negli-
gible unless high value feedback resistors are used. Since that
would result in slower response times than are possible, the
relatively low value of Rt in the AD844 will rarely be a signifi-
cant source of error.
A current applied to the inverting input is transferred to a
complementary pair of unity-gain current mirrors which deliver
the same current to an internal node (Pin 5) at which the full
output voltage is generated. The unity-gain complementary volt-
age follower then buffers this voltage and provides the load driv-
ing power. This buffer is designed to drive low impedance loads
such as terminated cables, and can deliver
±
50 mA into a 50
load while maintaining low distortion, even when operating at
supply voltages of only
±
6 V. Current limiting (not shown) en-
sures safe operation under short circuited conditions.
It is important to understand that the low input impedance at
the inverting input is locally generated, and does not depend on
feedback. This is very different from the “virtual ground” of a
conventional operational amplifier used in the current summing
mode which is essentially an open circuit until the loop settles.
In the AD844, transient current at the input does not cause
voltage spikes at the summing node while the amplifier is set-
tling. Furthermore, all of the transient current is delivered to the
slewing (TZ) node (Pin 5) via a short signal path (the grounded
base stages and the wideband current mirrors).
The current available to charge the capacitance (about 4.5 pF)
at TZ node, is
always proportional to the input error current,
and
the slew rate limitations associated with the large signal response
of op amps do not occur. For this reason, the rise and fall times
are almost independent of signal level. In practice, the input
current will eventually cause the mirrors to saturate. When using
±
15 V supplies, this occurs at about 10 mA (or
±
2200 V/µs).
Since signal currents are rarely this large, classical “slew rate”
limitations are absent.
This inherent advantage would be lost if the voltage follower
used to buffer the output were to have slew rate limitations. The
AD844 has been designed to avoid this problem, and as a result
the output buffer exhibits a clean large signal transient response,
free from anomalous effects arising from internal saturation.
Figure 27. Current to Voltage Converter
Circuit Description of the AD844
A simplified schematic is shown in Figure 28. The AD844 dif-
fers from a conventional op amp in that the signal inputs have
radically different impedance. The noninverting input (Pin 3)
presents the usual high impedance. The voltage on this input is
transferred to the inverting input (Pin 2) with a low offset volt-
–8–
REV. C