AD8362
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
COMM
CHPF
DECL
INHI
ACOM
VREF
VTGT
VPOS
VOUT
VSET
ACOM
CLPF
AD8362
TOP VIEW
(Not to Scale)
INLO
DECL
PWDN
COMM
Figure 2. Pin Configuration
Table 3. Pin Function Descriptions
Pin
Equivalent
Circuit
No.
1, 8
2
Mnemonic Description
COMM
CHPF
DECL
Common Connection. Connect via low impedance to system common.
Input HPF. Connect to common via a capacitor to determine 3 dB point of input signal high-pass filter.
Decoupling Terminals for INHI and INLO. Connect to common via a large capacitance to complete
input circuit.
3, 6
4, 5
INHI , INLO
Differential Signal Input Terminals. Input Impedance = 200 Ω. Can also be driven single-ended, in
which case, the input impedance reduces to 100 Ω.
Circuit A
7
9
PWDN
CLPF
Disable/Enable Control Input. Apply logic high voltage to shut down the AD8362.
Connection for Ground Referenced Loop Filter Integration (Averaging) Capacitor.
Analog Common Connection for Output Amplifier.
10, 16 ACOM
11
VSET
Setpoint Input. Connect directly to VOUT for measurement mode. Apply setpoint input to this pin for
controller mode.
RMS Output. In measurement mode, VOUT is normally connected directly to VSET.
Connect to 5 V Power Supply.
The logarithmic intercept voltage is proportional to the voltage applied to this pin. The use of a lower
target voltage increases the crest factor capacity. Normally connected to VREF.
General-Purpose Reference Voltage Output of 1.25 V. Usually connected only to VTGT.
Circuit B
Circuit C
12
13
14
VOUT
VPOS
VTGT
Circuit D
Circuit E
15
VREF
Rev. D | Page 7 of 32
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