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AD8362-EVALZ 参数 Datasheet PDF下载

AD8362-EVALZ图片预览
型号: AD8362-EVALZ
PDF下载: 下载PDF文件 查看货源
内容描述: 50 Hz至3.8 GHz的65分贝TruPwr ?探测器 [50 Hz to 3.8 GHz 65 dB TruPwr? Detector]
分类和应用:
文件页数/大小: 32 页 / 1029 K
品牌: ADI [ ADI ]
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AD8362  
OPERATION IN RF MEASUREMENT MODE  
The balun outputs must be ac-coupled to the input of the  
AD8362. The balun used in this example (M/A-COM ETC  
1.6-4-2-3) is specified for operation from 0.5 GHz to 2.5 GHz.  
BASIC CONNECTIONS  
Basic connections for operating the AD8362 in measurement  
mode are shown in Figure 47. While the AD8362 requires a  
single supply of nominally 5 V, its performance is essentially  
unaffected by variations of up to 10%.  
If a center-tapped, flux-coupled transformer is used, connect  
the center tap to the DECL pins, which are biased to the same  
potential as the inputs (~3.6 V).  
The supply is connected to the VPOS pin using the decoupling  
network also displayed in Figure 47. The capacitors used in this  
network must provide a low impedance over the full frequency  
range of the input and should be placed as close as possible to  
the VPOS pin. Two different capacitors are used in parallel to  
reduce the overall impedance because these have different reso-  
nant frequencies. The measurement accuracy is not critically  
dependent on supply decoupling because the high frequency  
signal path is confined to the relevant input pins. Lead lengths  
from both DECL pins to ground and from INHI/INLO to the  
input coupling capacitors should be as short as possible. All  
COMM pins should also connect directly to the ground plane.  
At lower frequencies where impedance matching is not neces-  
sary, the AD8362 can be driven from a low impedance differential  
source, remembering the inputs must be ac-coupled.  
Choosing Input Coupling Capacitors  
As noted, the inputs must be ac-coupled. The input coupling  
capacitors combine with the 200 ꢀ input impedance to create  
an input high pass corner frequency equal to  
f
HP = 1/(200 × π × CC)  
(12)  
Typically, fHP should be set to at least one tenth the lowest input  
frequency of interest.  
To place the device in measurement mode, connect VOUT to  
VSET and connect VTGT directly to VREF.  
Single-Ended Input Drive  
As previously noted, the input stages of the AD8362 are optimally  
driven from a fully balanced source, which should be provided  
wherever possible. In many cases, unbalanced sources can be  
applied directly to one or the other of the two input pins. The  
chief disadvantage of this driving method is a 10 dB to 15 dB  
reduction in dynamic range at frequencies above 500 MHz.  
DEVICE DISABLE  
The AD8362 is disabled by a logic high on the PWDN pin,  
which can be directly grounded for continuous operation.  
When enabled, the supply current is nominally 20 mA and  
essentially independent of supply voltage and input signal  
strength. When powered down by a logic low on PWDN,  
the supply current is reduced to 230 μA.  
Figure 48 illustrates one of many ways of coupling the signal  
source to the AD8362. Because the input pins are biased to  
about 3.6 V (for VS = 5 V), dc-blocking capacitors are required  
when driving from a grounded source. For signal frequencies  
>5 MHz, a value of 1 nF is adequate. While either INHI or  
INLO can be used, INHI is chosen here.  
RECOMMENDED INPUT COUPLING  
The full dynamic range of the AD8362, particularly at very  
high frequencies (above 500 MHz), is realized only when the  
input is presented to it in differential (balanced) form. In Figure 47,  
a transmission line balun is used at the input. Having a 1:4  
impedance ratio (1:2 turns ratio), the 200 Ω differential input  
resistance of the AD8362 becomes 50 Ω at the input to the balun.  
AD8362  
1
2
3
4
5
6
7
8
COMM  
CHPF  
DECL  
INHI  
16  
15  
14  
13  
12  
11  
10  
9
ACOM  
VREF  
VTGT  
VPOS  
VOUT  
VSET  
ACOM  
CLPF  
0.01µF  
1nF  
1nF  
1nF  
V
S
RF INPUT  
100  
5V @ 24mA  
INLO  
AD8362  
DECL  
PWDN  
COMM  
1:4 Z-RATIO  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
10  
9
COMM  
CHPF  
DECL  
INHI  
ACOM  
VREF  
VTGT  
VPOS  
VOUT  
VSET  
ACOM  
CLPF  
1nF  
C1  
C8  
0.1µF  
1000pF  
C10  
1000pF  
C4  
1nF  
C6  
SIGNAL  
INPUT  
Z = 50  
100pF  
C2  
1nF  
INLO  
V
OUT  
Figure 48. Input Coupling from a Single-Ended 50 Ω Source  
C7  
1nF  
C5  
DECL  
PWDN  
COMM  
100pF  
T1  
ETC1.6-4-2-3  
C3  
0.1µF  
Figure 47. Basic Connections for RF Power Measurement  
Rev. D | Page 19 of 32  
 
 
 
 
 
 
 
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