AD8361
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
VPOS
1
IREF
2
RFIN
3
PWDN
4
8
SREF
VRMS
FLTR
COMM
01088-C-004
AD8361
TOP VIEW
(Not to Scale)
VRMS
1
6
VPOS
7
6
5
AD8361
COMM
2
FLTR
3
01088-C-005
5
RFIN
TOP VIEW
(Not to Scale)
4
PWDN
Figure 4. 8-Lead MSOP
Figure 5. 6-Lead SOT-23
Table 3. Pin Function Descriptions
Pin No.
MSOP
1
2
3
4
Pin No.
SOT-23
6
N/A
5
4
Mnemonic
VPOS
IREF
RFIN
PWDN
Description
Supply Voltage Pin. Operational range 2.7 V to 5.5 V.
Output Reference Control Pin. Internal reference mode enabled when pin is left open; otherwise, this
pin should be tied to VPOS. Do not ground this pin.
Signal Input Pin. Must be driven from an ac-coupled source. The low frequency real input impedance
is 225 Ω.
Power-Down Pin. For the device to operate as a detector, it needs a logical low input (less than
100 mV). When a logic high (greater than V
S
− 0.5 V) is applied, the device is turned off and the supply
current goes to nearly zero (ground and internal reference mode less than 1 µA, supply reference
mode V
S
divided by 100 kΩ).
Device Ground Pin.
By placing a capacitor between this pin and VPOS, the corner frequency of the modulation filter is
lowered. The on-chip filter is formed with 27 pF||2 kΩ for small input signals.
Output Pin. Near rail-to-rail voltage output with limited current drive capabilities. Expected load
>10 kΩ to ground.
Supply Reference Control Pin. To enable supply reference mode, this pin must be connected to VPOS;
otherwise, it should be connected to COMM (ground).
5
6
7
8
2
3
1
N/A
COMM
FLTR
VRMS
SREF
Rev. C | Page 5 of 24
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