AD8362
PIN CONFIGURATION AND FUNCTION DESCRIPTION
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
COMM
CHPF
DECL
INHI
ACOM
VREF
VTGT
VPOS
VOUT
VSET
ACOM
CLPF
AD8362
TOP VIEW
INLO
(Not to Scale)
DECL
PWDN
COMM
Figure 2. Pin Configuration
Table 3. Pin Function Descriptions
Pin
Equivalent
Circuit
No.
1, 8
2
Mnemonic Description
COMM
CHPF
DECL
Common Connection. Connect via low impedance to system common.
Input HPF. Connect to common via a capacitor to determine 3 dB point of input signal high-pass filter.
Decoupling Terminals for INHI and INLO. Connect to common via a large capacitance to complete
input circuit.
3, 6
4
5
7
9
INHI
High Signal Input Terminal. Part of a differential input port with INLO.
Low Signal Input Terminal. Part of a differential input port with INHI.
Disable/Enable Control Input. Apply logic high voltage to shut down the AD8362.
Connection for loop filter integration (averaging) capacitor, the other pin of which is usually
grounded via a resistor to improve loop stability and response time.
Circuit A
Circuit A
INLO
PWDN
CLPF
10, 16 ACOM
Analog Common Connection for Output Amplifier.
11
VSET
The voltage applied to this pin sets the decibel value of the required RF input voltage that results in
zero current out of CLPF and thus the loop integrating capacitor.
Output of Error Amplifier. In measurement mode, normally connected directly to VSET.
Connect to 5 V Power Supply.
The logarithmic intercept voltage is proportional to the voltage applied to this pin. The use of a lower
target voltage increases the crest factor capacity.
General-Purpose Reference Voltage Output of 1.25 V (usually connected only to VTGT).
Circuit B
Circuit C
12
13
14
VOUT
VPOS
VTGT
Circuit D
Circuit E
15
VREF
Rev. B | Page 7 of 36
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