AD8346
INTERFACE TO AD9761 TXDAC®
Figure 28 shows a dc-coupled current output DAC interface.
The use of dual-integrated DACs, such as the AD9761 with
specified 0.02 dB and 0.004 dB gain and offset matching
characteristics, ensures minimum error contribution (over
temperature) from this portion of the signal chain. The use of a
precision thin-film resistor network sets the bias levels precisely
to prevent the introduction of offset errors, which increase LO
feedthrough. For instance, selecting resistor networks with a
0.1% ratio matching characteristics maintains 0.03 dB gain and
offset matching performance.
10 mA, giving a voltage swing of 0 V to 1 V (at the DAC
output). This results in a 0.5 V p-p swing at the I and Q inputs
of the AD8346 (resulting in a 1 V p-p differential swing).
Note that the ratio matching characteristics of the resistive
network, as opposed to its absolute accuracy, is critical in
preserving the gain and offset balance between the I and Q
signal path.
By applying small dc offsets to the I and Q signals from the
DAC, the LO suppression can be reduced from its nominal
value of −42 dBm to as low as −60 dBm while holding to
approximately −50 dBm over temperature (see Figure 12 for
a plot of LO feedthrough over temperature for an offset
compensated circuit).
Using resistive division, the dc bias level at the I and Q inputs
to the AD8346 is set to approximately 1.2 V. Each of the four
current outputs of the DAC delivers a full-scale current of
5V
+5V
634
500
Ω
Ω
0.1μF
500
Ω
DVDD DCOM
AVDD
VPS1
VPS2
100
100
Ω
Ω
500
Ω
IBBP
IBBN
IOUTA
IOUTB
I
LATCH
I
C
FILTER
2
×
DAC
VOUT
500
Ω
Σ
DAC
DATA
INPUTS
AD9761
LOIP
LOIN
500
500
Ω
500Ω
100
100
Ω
Ω
PHASE
SPLITTER
Ω
QBBP
QBBN
QOUTA
QOUTB
Q
DAC
LATCH
Q
C
FILTER
500
0.5V p-p EACH PIN
2
×
Ω
SELECT
MUX
CONTROL
AD8346
WITH V = 1.2V
WRITE
CM
CLOCK
SLEEP
FS ADJ REFIO
R
2k
SET
Ω
0.1μF
Figure 28. AD8346 Interface to AD9761 TxDAC
Rev. A | Page 12 of 20
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