AD8345
DVDD
DCOM
AVDD
VPS1
VPS2
IOUTA
IOUTB
IBBP
IBBN
"I"
DAC
LATCH
"I"
2⋅
210Ω
VOUT
Σ
140Ω
140Ω
DAC
DATA
INPUTS
AD9761
2⋅
LOIP
LOIN
PHASE
SPLITTER
QOUTA
QOUTB
QBBP
QBBN
LATCH
"Q"
"Q"
DAC
210Ω
SELECT
WRITE
MUX
CONTROL
140Ω
140Ω
AD8345
CLOCK
SLEEP
FS ADJ
REFIO
R
2kΩ
SET
0.1μF
Figure 31. AD8345/TxDAC Interface
The board is powered by a single supply (VS) in the range 2.7 V
to 5.5 V. The power supply is decoupled by 0.01 μF and 1000 pF
capacitors. The circuit closely follows the basic connection
schematic with SW1 in Position B. If SW1 is in Position A, the
enable pin (ENBL) is pulled to ground by a 10 kΩ resistor, and
the device is in its power-down mode.
SOLDERING INFORMATION
The AD8345 is packaged in a 16-lead TSSOP_EP package. For
optimum thermal conductivity, the exposed pad can be
soldered to the exposed metal of a ground plane. This results in
a junction-to-air thermal impedance (θJA) of 30°C/W. However,
soldering is not necessary for safe operation. If the exposed pad
is not soldered down, then the θJA is equal to 95°C/W.
All connectors are SMA-type. The I and Q inputs are dc-coupled to
allow a direct connection to a dual DAC with differential outputs.
Resistor pads are provided in case termination at the I and Q inputs
is required. The local oscillator input (LO) is terminated to approxi-
mately 50 Ω with an external 50 Ω resistor to ground. A 1:1 wide-
band transformer (ETC1-1-13) provides a differential drive to the
AD8345’s differential LO input.
EVALUATION BOARD
Figure 32 shows the schematic of the AD8345 evaluation board.
Note that uninstalled components are marked as open. This is a
4-layer board, with the two center layers used as ground plane,
and top and bottom layers used as signal and power planes.
R1
(OPEN)
R9
(OPEN)
AD8345
QBBP 16
1
2
3
4
5
6
7
8
IP
IN
QP
QN
IBBP
IBBN
COM3
COM1
LOIN
LOIP
15
14
13
12
11
10
9
QBBN
COM3
COM3
VPS2
R2
(OPEN)
R10
(OPEN)
R11
0Ω
C1
1000pF
VPOS
VOUT
C6
0.01μF
C5
1000pF
5
4
1
LO
R6
50Ω
C2
1000pF
T1
R12
0Ω
2
3
ETC1-1-13
VOUT
COM2
COM3
R14
R15
(OPEN)
C7
1000pF
(OPEN)
VPOS
VPS1
ENBL
C3
R7
0Ω
C4
1000pF
0.01μF
A
ENBL
R8
10kΩ
B
SW1
VPOS
Figure 32. Evaluation Board Schematic
Rev. B | Page 15 of 20
ADI [ ADI ]
