AD8321
ABSOLUTE MAXIMUM RATINGS*
PIN CONFIGURATION
SDATA
1
CLK
2
DATEN
3
GND
4
BYP1
5
20
VCC
19
VIN–
18
VIN+
17
VCC
Supply Voltage +V
S
Pins 7, 8, 9, 17, 20 . . . . . . . . . . . . . . . . . . . . . . . . . . . +11 V
Input Voltages
Pins 18, 19 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
±
0.5 V
Pins 1, 2, 3, 6 . . . . . . . . . . . . . . . . . . . . . . –0.8 V to +5.5 V
Internal Power Dissipation
Small Outline (R) . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.90 W
Operating Temperature Range . . . . . . . . . . . –40°C to +85°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Lead Temperature, Soldering 60 seconds . . . . . . . . . . +300°C
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
AD8321
16
GND
PD
6
TOP VIEW
15
GND
(Not to Scale)
14
BYP2
VCC
7
VCC
8
VCC
9
VOUT
10
13
GND
12
GND
11
GND
ORDERING GUIDE
Model
AD8321AR
AD8321AR-REEL
AD8321-EVAL
Temperature Range
–40°C to +85°C
–40°C to +85°C
Package Description
20-Lead SOIC
20-Lead SOIC
Evaluation Board
JA
Package Option
R-20
R-20
58°C/W*
58°C/W*
*Thermal Resistance measured on SEMI standard 4-layer board.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD8321 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
PIN FUNCTION DESCRIPTIONS
WARNING!
ESD SENSITIVE DEVICE
Pin
1
2
Function
SDATA
CLK
Description
Serial Data Input. This digital input allows for an 8-bit serial (gain) word to be loaded into the internal
register with the MSB (most significant bit) first.
Clock Input. The clock port controls the serial attenuator data transfer rate to the 8-bit master-slave
register. A Logic 0-to-1 transition latches the data bit and a 1-to-0 transfers the data bit to the slave.
This requires the input serial data word to be valid at or before this clock transition.
Data Enable Low Input. This port controls the 8-bit parallel data latch and shift register. A Logic 0-to-
1 transition transfers the latched data to the attenuator core (updates the gain) and simultaneously
inhibits serial data transfer into the register. A 1-to-0 transition inhibits the data latch (holds the previ-
ous gain state) and simultaneously enables the register for serial data load.
Common External Ground Reference.
V
CC
/2 Reference Pin. A dc output reference level that is equal to 1/2 of the supply voltage (VCC). This
port should be externally ac-decoupled (0.1
µF
capacitor). For external use of this reference voltage,
buffering is required.
Power-Down Low Logic Input. A Logic 0 powers down (shuts off) the power amplifier disabling the
output signal and enabling the reverse amplifier. A Logic 1 enables the output power amplifier and
disables the reverse amplifier.
Common Positive External Supply Voltage.
Output Signal Port. DC-biased to approximately V
CC
/2.
Internal Bypass. This pin must be externally ac-decoupled (0.1
µF
cap).
Noninverting Input. DC-biased to approximately V
CC
/2. For single-ended inverting operation, use
0.1
µF
decoupling capacitor between VIN+ and ground.
Inverting Input. DC-biased to approximately V
CC
/2. Should be ac-coupled with a 0.1
µF
capacitor.
–4–
REV. 0
3
DATEN
4, 11, 12,
13, 15, 16
5
GND
BYP1
6
PD
7, 8, 9, 17, 20
10
14
18
19
VCC
VOUT
BYP2
VIN+
VIN–
AD [ ANALOG DEVICES ]
