AD8321
LOGIC INPUTS (TTL/CMOS Logic)
(DATEN, CLK, SDATA, V
Parameter
Logic “1” Voltage
Logic “0” Voltage
Logic “1” Current (V
INH
= 5 V) CLK, SDATA,
DATEN
Logic “0” Current (V
INL
= 0 V) CLK, SDATA,
DATEN
Logic “1” Current (V
INH
= 5 V)
PD
Logic “0” Current (V
INL
= 0 V)
PD
CC
= +9 V; Full Temperature Range)
Min
2.1
0
0
–600
50
–250
Typ
Max
5.0
0.8
20
–100
190
–30
Unit
V
V
nA
nA
mA
mA
TIMING REQUIREMENTS
(Full Temperature Range, V
Parameter
Clock Pulsewidth (T
WH
)
Clock Period (T
C
)
Setup Time SDATA vs. Clock (T
DS
)
Setup Time
DATEN
vs. Clock (T
ES
)
Hold Time SDATA vs. Clock (T
DH
)
Hold Time
DATEN
vs. Clock (T
EH
)
Input Rise and Fall Times, SDATA,
DATEN,
Clock (T
R
, T
F
)
Specifications subject to change without notice.
T
DS
SDATA
VALID DATA WORD G1
MSB. . . .LSB
CC
= +9 V, T
R
= T
F
= 4 ns, f
CLK
= 8 MHz unless otherwise noted.)
Min
16.0
32.0
5.0
15.0
5.0
3.0
10
Typ
Max
Unit
ns
ns
ns
ns
ns
ns
ns
VALID DATA WORD G2
T
C
T
WH
CLK
T
ES
DATEN
T
EH
8 CLOCK CYCLES
GAIN TRANSFER (G1)
T
OFF
PD
T
GS
GAIN TRANSFER (G2)
T
ON
ANALOG
OUTPUT
SIGNAL AMPLITUDE (p-p)
PEDESTAL
Figure 2. Serial Interface Timing
VALID DATA BIT
SDATA MSB
MSB-1
MSB-2
T
DS
T
DH
CLK
Figure 3. SDATA Timing
REV. A
–3–
AD [ ANALOG DEVICES ]
