AD8315
SPECIFICATIONS
V
S
= 2.7 V, T = 25°C, 52.3 Ω termination on RFIN, unless otherwise noted.
Table 1.
Parameter
OVERALL FUNCTION
Frequency Range
Input Voltage Range
Equivalent dBm Range
Logarithmic Slope
Logarithmic Intercept
2
Equivalent dBm Level
RF INPUT INTERFACE
Input Resistance
Input Capacitance
OUTPUT
Minimum Output Voltage
Maximum Output Voltage
vs. Temperature
General Limit
Output Current Drive
Output Buffer Noise
Output Noise
Small Signal Bandwidth
Slew Rate
Response Time
SETPOINT INTERFACE
Nominal Input Range
Logarithmic Scale Factor
Input Resistance
Slew Rate
ENABLE INTERFACE
Logic Level to Enable Power
Input Current when Enable
High
Logic Level to Disable Power
Enable Time
Disable Time
Power-On/Enable Time
Conditions
To meet all specifications
±1 dB log conformance, 0.1 GHz
0.1 GH
0.1 GHz
Pin RFIN
0.1 GHz
0.1 GHz
Pin VAPC
V
SET
≤ 200 mV, ENBL high
ENBL low
R
L
≥ 800 Ω
85°C, V
POS
= 3 V, I
OUT
= 6 mA
2.7 V ≤ V
POS
≤ 5.5 V, R
L
= ∞
Source/Sink
RF input = 2 GHz, 0 dBm, f
NOISE
= 100 kHz, C
FLT
= 220 pF
0.2 V to 2.6 V swing
10% to 90%, 1.2 V step (V
SET
), open loop
FLTR = open, see Figure 26
Pin VSET
Corresponding to central 50 dB
Min
0.1
−57
−44
21.5
−79
−66
Typ
Max
2.5
−11
+2
25.5
−64
−51
Unit
GHz
dBV
dBm
mV/dB
dBV
dBm
kΩ
pF
0.3
2.6
V
POS
− 0.1
5/200
25
130
30
13
150
0.25
43.5
100
16
Pin ENBL
1.8
20
0.8
5
9
3
200
V
POS
V
μA
V
μs
μs
μs
ns
1.4
V
V
V
V
V
mA/μA
nV√Hz
nV/√Hz
MHz
V/μs
ns
V
dB/V
kΩ
V/μs
24
−70
−57
2.8
0.9
0.25
2.45
2.54
0.27
0.02
Time from ENBL high to V
APC
within 1% of final value,
V
SET
≤ 200 mV, refer to Figure 23
Time from ENBL low to V
APC
within 1% of final value,
V
SET
≤ 200 mV, refer to Figure 23
Time from VPOS/ENBL high to V
APC
within 1% of final value,
V
SET
≤ 200 mV, refer to Figure 28
Time from VPOS/ENBL low to V
APC
within 1% of final value,
V
SET
≤ 200 mV, refer to Figure 28
4
8
2
100
Rev. C | Page 3 of 24
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