AD8307
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
INM
1
COM
2
OFS
3
8
INP
VPS
01082-002
AD8307
7
6
ENB
TOP VIEW
(Not to Scale)
5
INT
OUT
4
Figure 2. Pin Configuration
Table 3. Pin Function Descriptions
Pin No.
1
2
3
4
5
6
7
8
Mnemonic
INM
COM
OFS
OUT
INT
ENB
VPS
INP
Description
Signal Input Minus Polarity. Normally at V
POS
/2.
Common Pin (Usually Grounded).
Offset Adjustment. External capacitor connection.
Logarithmic (RSSI) Output Voltage. R
OUT
= 12.5 kΩ.
Intercept Adjustment, ±3 dB (see the Slope and Intercept Adjustments section).
CMOS-Compatible Chip Enable. Active when high.
Positive Supply: 2.7 V to 5.5 V.
Signal Input Plus Polarity. Normally at V
POS
/2. Due to the symmetrical nature of the response, there is no special
significance to the sign of the two input pins. DC resistance from INP to INM = 1.1 kΩ.
Rev. C | Page 5 of 24
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