AD824
WAFER TEST LIMITS
(@ V = +5.0 V, V
S
CM
= 0 V, T
A
= +25 C unless otherwise noted)
Conditions
Limit
1.0
12
20
–0.2 to 3.0
66
70
15
4.975
25
600
Units
mV max
pA max
pA
V min
dB min
µV/V
V/mV min
V min
mV max
µA
max
Parameter
Offset Voltage
Input Bias Current
Input Offset Current
Input Voltage Range
Common-Mode Rejection Ratio
Power Supply Rejection Ratio
Large Signal Voltage Gain
Output Voltage High
Output Voltage Low
Supply Current/Amplifier
Symbol
V
OS
I
B
I
OS
V
CM
CMRR
PSRR
A
VO
V
OH
V
OL
I
SY
V
CM
= 0 V to 2 V
V = + 2.7 V to +12 V
R
L
= 2 kΩ
I
SOURCE
= 20
µA
I
SINK
= 20
µA
V
O
= 0 V, R
L
=
∞
NOTE
Electrical tests and wafer probe to the limits shown. Due to variations in assembly
methods and normal yield loss, yield after packaging is not guaranteed for
standard product dice. Consult factory to negotiate specifications based on dice
lot qualifications through sample lot assembly and testing.
DICE CHARACTERISTICS
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
±
18 V
Input Voltage . . . . . . . . . . . . . . . . . . . . . . . –V
S
– 0.2 V to +V
S
Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . .
±
30 V
Output Short Circuit Duration to GND . . . . . . . . . Indefinite
Storage Temperature Range
N, R Package . . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Operating Temperature Range
AD824A, B . . . . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C
Junction Temperature Range
N, R Package . . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Lead Temperature Range (Soldering, 60 sec) . . . . . . . +300°C
Package Type
14-Pin Plastic DIP (N)
14-Pin SOIC (R)
16-Pin SOIC (R)
θ
JA2
76
120
92
θ
JC
33
36
27
Units
°C/W
°C/W
°C/W
ABSOLUTE MAXIMUM RATINGS
1
AD824 Die Size 0.70 X 0.130 inch, 9,100 sq. mils.
Substrate (Die Backside) Is Connected to V+. Transistor
Count, 143.
V
CC
I5
R1
R2
R9
I6
Q18
Q29
NOTES
1
Absolute maximum ratings apply to both DICE and packaged parts unless
otherwise noted.
2
θ
JA
is specified for the worst case conditions, i.e.,
θ
JA
is specified for device in socket
for P-DIP packages;
θ
JA
is specified for device soldered in circuit board for SOIC
package.
Q21 Q27
Q4
+IN
J1
J2
Q5
Q19
Q7
R13
Q22
R7
Q23
C4
V
OUT
Q20
Q6
C3
ORDERING GUIDE
Model
AD824AN
AD824BN
AD824AR
AD824AR-3V
AD824AN-3V
AD824AR-14
AD824AR-14-3V
AD824AR-16
AD824AChips
Temperature
Range
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
+25°C
Package Option
14-Pin Plastic DIP
14-Pin Plastic DIP
14-Pin SOIC
14-Pin SOIC
14-Pin Plastic DIP
14-Pin SOIC
14-Pin SOIC
16-Pin SOIC
DICE
–IN
R15
C2
Q24 Q25
Q8
C1
Q2
R12
I1
R14
Q28
I2
I3
V
EE
I4
R17
Q26
Q3
Q31
Figure 1. Simplified Schematic of 1/4 AD824
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
WARNING!
accumulate on the human body and test equipment and can discharge without detection.
Although the AD824 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
ESD SENSITIVE DEVICE
precautions are recommended to avoid performance degradation or loss of functionality.
REV. A
–5–
AD [ ANALOG DEVICES ]
