Data Sheet
A 3.3 V/5 V PRECISION SAMPLE-AND-HOLD
AMPLIFIER
In battery-powered applications, low supply voltage operational
amplifiers are required for low power consumption. Also, low
supply voltage applications limit the signal range in precision
analog circuitry. Circuits like the sample-and-hold circuit
shown in Figure 37 illustrate techniques for designing precision
analog circuitry in low supply voltage applications. To maintain
high signal-to-noise ratios (SNRs) in a low supply voltage
application requires the use of rail-to-rail, input/output
operational amplifiers. This design highlights the ability of the
to operate rail-to-rail from a single 3 V/5 V supply, with
the advantages of high input impedance. The
a quad
JFET-input op amp, is well suited to sample-and-hold circuits
due to its low input bias currents (3 pA, typical) and high input
impedances (3 × 10
13
Ω, typical). The
also exhibits very
low supply currents so the total supply current in this circuit is
less than 2.5 mA.
3.3V/5V
R1
50kΩ
3.3V/5V
0.1µF
4
AD824
A design consideration in sample-and-hold circuits is voltage
droop at the output caused by op amp bias and switch leakage
currents. By choosing an JFET op amp and a low leakage CMOS
switch, this design minimizes droop rate error to better than
0.1 µV/µs in this circuit. Higher values of CH will yield a lower
droop rate. For best performance, CH and C2 should be
polystyrene, polypropylene or Teflon capacitors.
These types of capacitors exhibit low leakage and low dielectric
absorption. Additionally, 1% metal film resistors were used
throughout the design.
In the sample mode, SW1 and SW4 are closed, and the output is
V
OUT
= −V
IN
. The purpose of SW4, which operates in parallel
with SW1, is to reduce the pedestal, or hold step, error by
injecting the same amount of charge into the noninverting
input of A3 that SW1 injects into the inverting input of A3. This
creates a common-mode voltage across the inputs of A3 and is
then rejected by the CMR of A3; otherwise, the charge injection
from SW1 creates a differential voltage step error that appears at
V
OUT
. The pedestal error for this circuit is less than 2 mV over
the entire 0 V to 3.3 V/5 V signal range. Another method of
reducing pedestal error is to reduce the pulse amplitude applied
to the control pins. To control the
only 2.4 V are
required for the on state and 0.8 V for the off state. If possible,
use an input control signal whose amplitude ranges from 0.8 V
to 2.4 V instead of a full range 0 V to 3.3 V/5 V for minimum
pedestal error.
Other circuit features include an acquisition time of less than
3 µs to 1%; reducing CH and C2 will speed up the acquisition
time further, but an increased pedestal error will result. Settling
time is less than 300 ns to 1%, and the sample-mode signal BW
is 80 kHz.
+
V
–
OUT
AD824
3
2
A1
11
1
R2
50kΩ
FALSE GROUND (FG)
R4
2kΩ
3.3V/5V
13
15
14
ADG513
R5
2kΩ
SW2
16
10
11
AD824
5
6
SW3
9
FG
7
2
SW1
1
10
9
7
SW4
8
6
3
CH
500pF
A2
A3
8
AD824
C2
500pF
AD824
12
FG
14
4
5
13
Figure 37. 3.3 V/5.5 V Precision Sample-and-Hold Circuit
In many single supply applications, the use of a false ground
generator is required. In this circuit, R1 and R2 divide the
supply voltage symmetrically, creating the false ground voltage
at one-half the supply. Amplifier A1 then buffers this voltage
creating a low impedance output drive. The sample-and-hold
circuit is configured in an inverting topology centered around
this false ground level.
Rev. E | Page 15 of 16
00875-037
SAMPLE/
HOLD
A4
FG
The
was chosen for its ability to work with 3 V/5 V
supplies and for having normally open and normally closed
precision CMOS switches on a dielectrically isolated process.
SW2 is not required in this circuit; however, it was used in
parallel with SW3 to provide a lower R
ON
analog switch.
AD [ ANALOG DEVICES ]
